Junction Temperature and the Thermal Resistance Network

A processor does not have a temperature. It has a distribution, with the arithmetic units hottest, the cache cooler, and the edges cooler still, and the distribution moves as the workload moves. The number that matters for reliability and for correct timing is the peak junction temperature, the temperature of the silicon at the hottest point, and the standard way to compute it is to pretend the whole path from silicon to air is a series of resistors.

The analogy is exact enough to be useful and loose enough to mislead. Heat flow is analogous to current, temperature difference to voltage, and thermal resistance to electrical resistance, with the units of kelvin per watt. The analogy holds for steady state and for linear conduction; it breaks wherever the heat flow is not one-dimensional, which is most of the interesting cases.

The resistance stack, term by term

For a packaged part with a heat sink, the path from junction to ambient has four resistances in series, and the junction temperature is

$$T_j = T_a + P , (\theta_{jc} + \theta_{\text{TIM}} + \theta_{hs} + \theta_{sa})$$

where $P$ is the dissipated power and each $\theta$ is a temperature rise per watt. The subscripts name the interfaces: junction to case, case through the thermal interface material, heat sink spreading and conduction, and sink to ambient.

The junction-to-case term is set by the die, the die attach, and the package lid. Silicon conducts heat well, around 150 W/(m·K), so a die 0.7 mm thick with a uniform heat flux has a through-thickness resistance per unit area of about 4.7 mm²·K/W, which is small. The die attach and the lid matter more: a solder attach conducts far better than a polymer one, and a thin lid of copper conducts better than a thick one of lower-conductivity material only up to the point where spreading dominates.

The thermal interface material is usually the largest single term per unit area, and the one most often underestimated. A polymer gap filler might conduct 3 W/(m·K); a good phase-change material or a metal-filled grease might reach 5 to 8; a solder TIM is an order of magnitude better but brings mechanical stress. The resistance of a layer is $t/(kA)$, so a 25 µm layer of 3 W/(m·K) material over a 1 cm² area is 0.083 K/W, and a 100 µm layer of the same material is 0.33 K/W. Halving the bond line halves that, which is why mounting pressure and surface flatness are specified as tightly as the material itself.

The sink-to-ambient term is not a material property at all. It is a property of the airflow, and it is covered in airflow and fan curves. What matters here is that it is in series with everything else and is usually the largest term, so the junction temperature is dominated by the cooling system rather than by the package.

A worked budget

Take a part dissipating 95 W, an ambient of 35 °C inside the chassis, and a junction limit of 100 °C. The total budget is 65 K, so the total resistance must be at most 0.68 K/W. Suppose the sink-to-ambient resistance is 0.15 K/W at the design airflow, the sink’s own conduction and spreading resistance is 0.08, the TIM is 0.10, and the junction-to-case is 0.12. The sum is 0.45 K/W, which gives a junction temperature of 78 °C, leaving 22 K of margin.

Now raise the power to 120 W and the same stack gives 89 °C. The margin is gone. This is the arithmetic that governs every cooling decision: the resistance is fixed by geometry once the part is built, so the only levers are power and ambient, and both are set by other parts of the system.

The margin is not spare capacity to be used up. It covers the difference between the assumed and the actual airflow, the degradation of the TIM over thermal cycling, dust on the fins, and the fact that the junction-to-case resistance quoted in a datasheet is measured under a specified boundary condition that the real board does not reproduce. A design that computes to the limit at nominal conditions will exceed it in the field.

Spreading, the term the one-dimensional model omits

The series model assumes the heat flux is uniform across each interface. It is not. A die might be 1 cm² while the heat sink base is 30 cm², and the heat must spread laterally through the base to reach the fins. That lateral flow has its own resistance, called the spreading resistance, and it depends on the ratio of source to sink area and on the base thickness.

For a circular source of radius $a$ on a semi-infinite solid, the spreading resistance is approximately $1/(4ka)$, so a 1 cm² source on copper has a spreading resistance of order 0.1 K/W. That is comparable to the other terms in the stack, and it grows as the source shrinks: halving the source dimension doubles the spreading resistance. It is the reason a small, high-power die needs a thick copper base or a vapour chamber rather than a plain aluminium plate, and the reason heat spreaders are designed for lateral transport rather than for fin area.

Spreading also creates the hot spot the junction limit is written against. The peak junction temperature is not the average over the die plus the series drop; it is the local value at the densest power region, and it can exceed the average by 10 to 20 K on a part with strongly non-uniform activity. Thermal analysis therefore has two outputs, an average and a peak, and the peak is what the reliability rules use.

Transient behaviour: the same network with capacitors

Steady state is the easy case. A processor’s power changes on a microsecond timescale, and the junction temperature does not follow instantly, because the heat capacity of the silicon, the package, and the sink stores energy. The transient network adds a capacitor at each node, and the response to a power step is a sum of exponentials with time constants set by each $R$ and $C$ pair.

The constants are widely separated, which is what makes the behaviour manageable. The die’s own thermal time constant, set by its heat capacity and the resistance to the case, is on the order of milliseconds. The package and TIM add tens of milliseconds. The heat sink adds seconds. A burst of activity lasting 100 µs raises the junction temperature by a small fraction of what the same power sustained would produce, because the heat has not had time to leave the die.

Manufacturers publish this as a transient thermal impedance curve, $\Delta T_j$ per watt as a function of pulse duration, usually for a specified duty cycle. The curve is the thermal analogue of an impedance magnitude versus frequency, and it is what a burst-power specification should be checked against. A part rated for 95 W continuously may tolerate several hundred watts for a millisecond, and the limit is not the average power but the peak junction temperature reached at the end of the pulse.

def rc_step(power, r, c, t):
    """Junction rise after a power step into a single R-C thermal node."""
    return power * r * (1.0 - pow(2.718281828, -t / (r * c)))

# die alone: 0.12 K/W, 0.05 J/K  -> tau = 6 ms
for ms in (0.1, 1, 6, 60):
    print(ms, round(rc_step(95, 0.12, 0.05, ms / 1000), 2), "K")

The single-node model is a lower bound on the real rise, because the real structure has distributed capacitance and the fast nodes heat before the slow ones. Real transient curves are the sum of several such terms, and the fast terms are the ones that matter for short bursts.

Where the model stops being predictive

The resistance network is a linear model, and heat transfer to air is not linear. Radiation scales with the fourth power of absolute temperature and becomes a meaningful fraction of the total only at high sink temperatures or in still air; convection depends on the flow regime and on whether the flow is laminar or turbulent, and the transition changes the exponent in the correlation. A sink characterised at one airflow does not scale to another by a simple factor.

Contact resistance between the sink and the package is another non-linearity. It depends on pressure, on surface roughness, and on how many times the assembly has been cycled, and it can change by a factor of two across the life of a product. Designs that pass at first article and fail after a thousand cycles are usually failing at that interface.

The largest error, though, is in the power number itself. The resistance stack is only as good as the $P$ that goes into it, and $P$ depends on the workload, on the voltage and frequency the part is running at, and on the temperature itself through leakage. That last dependence closes a loop, and the loop is the subject of leakage and electrothermal feedback.