Leakage Power and the Electrothermal Feedback Loop

Dynamic power is the part of a processor’s consumption that the workload controls: it scales with activity, with frequency, and with the square of voltage. Leakage is the part that does not care what the processor is doing. It flows through every transistor that is nominally off, it is present at idle, and it grows exponentially with temperature. The combination is what makes thermal design hard at advanced process nodes, because power determines temperature and temperature determines power.

Where off-state current comes from

A MOSFET that is off still conducts, for reasons that are all short-channel effects to some degree.

Subthreshold conduction is the dominant term. Below threshold, the channel is not inverted but the carrier concentration at the source end still follows a Boltzmann distribution, so the drain current varies exponentially with gate voltage over several decades. The inverse subthreshold slope is the gate voltage needed to change the current by a decade, and a well-behaved device at room temperature reaches about 60 mV/decade, set by $kT/q$ and the body factor. That 60 mV/decade is a thermal limit: the carriers are distributed in energy according to temperature, so no gate geometry can make the transition sharper than the Boltzmann tail allows. It is also the reason threshold voltage cannot simply be lowered to raise drive current: each 60 mV of reduction multiplies leakage by ten.

Gate leakage is tunnelling through the gate dielectric. As oxide thickness fell to a couple of nanometres, direct tunnelling became significant, and it grows exponentially with decreasing thickness. The industry response was to stop thinning silicon dioxide and move to higher-permittivity dielectrics, which achieve the same capacitance with a physically thicker film, so the tunnelling path is longer. That change is why the gate stack at advanced nodes is a composite rather than a single oxide.

Junction leakage is the reverse-biased drain and source diode current, which includes band-to-band tunnelling in the high-field region near the drain. It is smaller than subthreshold conduction in most designs but grows with doping and with temperature.

The three terms have different temperature dependences, and all of them increase. Subthreshold conduction is the steepest: the current at fixed gate voltage rises by roughly a factor of two for every 10 K near room temperature, because the threshold voltage falls with temperature (about -1 to -2 mV/K) and the subthreshold slope worsens. A 40 K rise from 40 °C to 80 °C therefore multiplies leakage by something like 16, before any change in the supply. The exponential temperature coefficient is what makes the feedback loop below possible, and the thermal resistance it works against is the series stack from junction to air.

The loop, written as an equation

Let $P_{\text{dyn}}$ be the workload-dependent power, roughly independent of temperature at fixed voltage and frequency. Let leakage be

$$P_{\text{leak}}(T) = P_{\text{leak},0} , e^{\beta (T - T_0)}$$

with $\beta$ around 0.05 to 0.07 per kelvin, corresponding to the doubling every 10 to 14 K. The junction temperature follows the thermal resistance:

$$T = T_a + \theta , (P_{\text{dyn}} + P_{\text{leak}}(T))$$

Substituting gives a transcendental equation in $T$, and its behaviour is the whole story:

$$T = T_a + \theta P_{\text{dyn}} + \theta P_{\text{leak},0} e^{\beta (T - T_0)}$$

The right side is an exponential in $T$ with a slope of $\theta P_{\text{leak},0} \beta e^{\beta(T-T_0)}$. The left side has slope 1. If the exponential’s slope is less than 1 everywhere, there is exactly one solution and the system is stable. If the slope exceeds 1 at the operating point, no solution exists and the temperature rises without bound, which is thermal runaway.

The stability condition is therefore $\theta , \beta , P_{\text{leak}} < 1$. With $\beta = 0.06$/K, runaway requires $\theta P_{\text{leak}} > 16.7$ K, meaning the leakage alone must produce more than about 17 K of self-heating before the loop becomes unstable. A part with 0.2 K/W of total thermal resistance and 5 W of leakage produces 1 K of self-heating, which is safe; the same part with 40 W of leakage produces 8 K, which is closer but still safe; at 90 W of leakage it would be marginal.

The condition is worth reading as a design rule. Thermal resistance must be low enough that the leakage power’s self-heating stays well below $1/\beta$. Because leakage rises steeply with temperature and with voltage, a design that is stable at nominal voltage can become unstable at the elevated voltage used for overclocking, which is one reason overclocking a part with a marginal cooler can end in a thermal event rather than in a throttled slowdown.

Why leakage became a first-order term

In older processes, leakage was a rounding error on the dynamic power. The ratio changed because threshold voltage had to fall with supply voltage to keep drive current, and because gate oxides thinned. At the 90 nm generation and beyond, leakage became a visible fraction of total power at full activity and the dominant term at idle.

The design response came in several forms. Multi-threshold libraries put high-threshold cells on non-critical paths, where the slower switching is acceptable and the leakage is orders of magnitude lower; the cost is more library variants, more synthesis constraints, and more corners to sign off. Power gating inserts a high-threshold switch between a block and its supply and turns the block off entirely when idle, which removes leakage at the price of state retention logic and a wake-up latency of microseconds. Body biasing raises the threshold by reverse-biasing the well, trading speed for leakage dynamically. And dynamic voltage and frequency scaling reduces the supply when the workload allows, which cuts leakage both through the lower voltage and through the lower temperature that follows.

The economics of these techniques are all the same: leakage is a function of the fraction of time a block is idle, so a block that is active most of the time gains little from power gating, while one that is idle most of the time gains almost everything.

Temperature is not uniform, and neither is leakage

The loop operates locally as well as globally. A region of the die that runs hotter leaks more, which makes it hotter still, and the result is a hot spot that is warmer than a global energy balance would predict. The local loop has a smaller thermal resistance to its neighbours than to the ambient, so it is usually stable, but the hot spot’s temperature can exceed the die average by 10 to 20 K and it is the number the reliability rules use.

This is the mechanism behind the observation that a chip’s power depends on its own temperature distribution, not just on its total. Two workloads with identical average activity can produce different total power if they concentrate activity differently, because the concentrated one runs hotter and leaks more. It also means that power measurements taken on a cold part overstate the efficiency of the cooling solution: as the part warms, the power rises toward the value the cooler must actually remove.

The local loop has a second-order effect on timing. Leakage-induced heating raises the temperature, which raises resistance and lowers drive current, which slows the circuit; a path that is critical at one temperature may not be critical at another, and the sign of the change depends on whether the path is dominated by interconnect or by transistors. Static timing analysis runs at multiple temperature corners for this reason.

Measurement, and why the numbers are hard to pin down

Leakage is specified at a temperature, and the specification is usually a worst-case value at the maximum junction temperature with a process corner applied. That number can be an order of magnitude above the typical value at room temperature, and both are real: the design must survive the worst case, while the thermal solution is usually sized for something between.

The measurement itself is awkward because leakage cannot be separated from dynamic power by looking at total current. The standard technique is to stop the clock and measure the current with the circuit in a known state, which captures subthreshold and gate leakage but not the switching component; the result depends on the state the circuit was stopped in, since different input vectors leave different numbers of transistors off. Leakage is therefore state-dependent, and the worst-case vector is a separate analysis.

Temperature measurement has its own problem. An on-die thermal sensor is a diode or a transistor biased at a known current, and its reading is the temperature at the sensor’s location, which is not the hot spot. Sensors are placed where they are representative, and the difference between the sensor reading and the peak junction temperature is a calibration constant that must be characterised per design.

The limit this imposes

The same loop is what the throttling controllers are protecting against, and the constraint below is the reason their response is not simply a fixed temperature trip. The loop sets a hard constraint on how far voltage can be scaled down and how far power density can be scaled up. Below some supply voltage the circuit’s delay rises faster than the voltage reduction saves energy, and the leakage fraction grows because the threshold cannot fall as fast as the supply. That minimum-energy point is the reason voltage scaling stopped being a free win, and it is the same arithmetic that ended Dennard scaling, viewed from the leakage side rather than the dynamic side.

The practical consequence for thermal design is that the power a cooler must remove is not a fixed specification. It is a function of the cooling solution itself, and the function is steep. A cooler that holds the junction 10 K lower removes less power than one that lets it run hotter, so comparing two cooling solutions by their rated wattage alone is misleading: the comparison must be at the same junction temperature, and the part’s own leakage curve must be part of the calculation.