Energy-Optimal Operating Points and the Shape of DVFS

The energy a circuit spends on an operation is the product of its power and the time the operation takes. Reducing the supply voltage reduces power quadratically but increases delay, so the time rises, and the two effects nearly cancel. What is left over is a residual dependence that determines whether scaling voltage saves energy or wastes it, and the location of that boundary is the central design fact of dynamic voltage and frequency scaling.

The relationship is worth deriving, because the intuition that “lower voltage is more efficient” is only true within a range, and the range ends sooner than most people expect.

The two terms in the energy per operation

Consider a circuit whose critical path delay is dominated by transistor current charging capacitance. In the simplified model where drain current is proportional to $(V - V_{th})^2$ above threshold, the delay through a path of capacitance $C$ and effective drive $K$ is

$$t_d \approx \frac{C , V}{K , (V - V_{th})^2}$$

and the dynamic energy per switching event is $E = C V^2$. The energy per operation is the energy of one event multiplied by the number of events per operation, which does not change with frequency; what changes with frequency is how long the operation takes, and therefore how much leakage energy accumulates during it.

The total energy per operation is therefore

$$E_{\text{op}} = E_{\text{dyn}} + P_{\text{leak}} , t_{\text{op}} = C V^2 + P_{\text{leak}}(V, T) \cdot N , t_d$$

where $N$ is the number of cycles the operation takes. As $V$ falls toward $V_{th}$, the delay grows without bound and the leakage term grows with it, while the dynamic term falls. The sum has a minimum somewhere above $V_{th}$, and below that minimum further voltage reduction costs energy rather than saving it.

The location of the minimum depends on the ratio of leakage to dynamic power. In a process where leakage is a small fraction of total power, the minimum sits close to $V_{th}$ and voltage scaling is a large win. Where leakage is comparable to dynamic power at nominal voltage, the minimum is well above $V_{th}$ and the win is small. This is the quantitative form of the statement that leakage ended the free lunch: as processes scaled, the leakage term in the energy expression grew until the minimum moved up and the useful range of voltage shrank.

Frequency cannot move independently

A supply voltage is only valid at a frequency the circuit can meet at that voltage. Running at a lower frequency than the voltage allows wastes energy, because the dynamic energy per event is fixed by the voltage and the operation takes longer than it needs to. Running at a higher frequency than the voltage allows produces timing failures.

The operating states available to a processor are not a continuous plane of voltage and frequency but a set of points along a curve: for each voltage, the maximum frequency that closes timing across all corners. That curve is the frequency-voltage characteristic, and it is roughly linear at high voltage and steeply rising as voltage approaches threshold, because the delay model above diverges there. It is also the input to the thermal and power limiters, which can only select among the states it defines.

The practical operating points are a discrete subset of that curve, the P-states in the ACPI vocabulary. Each state specifies a frequency and the voltage that supports it, and the platform’s firmware exposes the table. A part with a wide voltage range may have a dozen or more states; a part optimised for a narrow range may have three. Transitions between states involve changing the PLL ratio and the regulator setpoint, and the sequence matters: raising frequency before voltage causes a timing failure, so voltage must rise first and fall last, with a delay between the two long enough for the regulator to settle.

The cubic illusion

There is a widely repeated claim that power scales with the cube of frequency, derived from $P \propto V^2 f$ and the assumption that $V \propto f$. The assumption is wrong at low frequency, where the voltage cannot fall below a floor, and it is wrong at high frequency, where the voltage must rise faster than linearly to keep the circuit working. The cube law is a reasonable approximation in the middle of the range and a poor one at either end.

The consequence is that energy per operation, which is power divided by frequency, scales as $V^2$ if the voltage tracks frequency, and therefore as roughly $f^2$ in the same middle range. Halving the frequency in that range quarters the energy per operation, so the same work takes twice as long for a quarter of the dynamic energy, a saving of a factor of four for the task. Outside that range the saving is smaller, and below the minimum described above it becomes negative.

The “race to idle” argument rests on this. If a task has a fixed amount of work and the machine would otherwise idle, running at maximum frequency finishes the task sooner and lets the machine enter a low-power state, and the energy saved during the idle period can exceed the extra energy spent running fast. The argument is valid only if the idle state’s power is genuinely low and the transition cost is small; if the idle power is a significant fraction of active power, or if entering and leaving the state costs milliseconds, running slowly throughout is better.

Where the workload changes the answer

The leakage term in that expression is not a constant, since it rises with the junction temperature, which the operating point itself partly sets; electrothermal feedback is the mechanism. The energy-optimal operating point is a property of the workload, not just of the silicon. A compute-bound workload spends its time in the core, and its energy per operation follows the analysis above. A memory-bound workload spends its time waiting, and reducing the core frequency barely changes its execution time while reducing the core’s voltage still saves its dynamic energy; the optimum for such a workload is often the lowest available state, because the memory system’s energy is unaffected by the core’s voltage.

An I/O-bound workload with latency requirements is different again: the constraint is response time, and the optimum is the lowest state that meets it, which may be far above the energy minimum. This is why the same processor in a phone and in a server runs at very different points for the same silicon: the constraint is different, and the energy minimum is not the operating point in either case.

The mixed case is the common one, and it is handled by a governor that estimates the workload’s utilisation and picks a state. The estimator’s error is the dominant term in the governor’s effectiveness: a governor that overestimates utilisation runs too fast and wastes energy, and one that underestimates runs too slow and misses deadlines. Both failure modes are visible in the energy-per-task curve as a flat region around the true optimum, which is fortunate, because it means a moderately wrong governor costs little.

The cost of changing states

A state transition is not free. The regulator must slew its output, the PLL must relock, and the domains that are on a separate clock must be resynchronised. The total is typically tens of microseconds, and during it the processor may be stalled or running at an intermediate state.

The transition cost sets a minimum residency time for a state to be worth entering. If a state saves 20 percent of power but costs 50 µs to enter and leave, a period of activity shorter than a few hundred microseconds gains nothing. This is why governors apply hysteresis and why very short idle periods are handled by a shallower sleep state or by clock gating rather than by a voltage change.

Clock gating is the cheaper mechanism and it operates at a much finer grain. A block whose clock is stopped consumes only leakage, and the transition costs a few cycles. The hierarchy is therefore: clock gating for idle periods of nanoseconds to microseconds, voltage and frequency scaling for microseconds to milliseconds, and power gating or sleep states for milliseconds and above. Each level has a lower floor but a higher entry cost, and the governor’s job is to pick the level that matches the expected idle duration.

Measurement, and the trap in it

Energy is measured by integrating power over time, and power is measured either by a sense resistor on the input rail or by the processor’s own energy counters. Both have systematic errors that matter for comparing operating points.

A sense resistor on the input measures everything downstream, including the regulator’s losses, which change with the operating point: at low voltage the regulator’s efficiency is different, and the conversion loss can be a substantial fraction of the total. A measurement that stops at the regulator’s output understates the system energy at low voltage, because it excludes the conversion loss that the low voltage makes worse.

The processor’s own counters estimate energy from activity and voltage, and they are calibrated at a few operating points. Their error grows away from those points, particularly at low voltage where leakage’s share is larger and the model’s leakage term is less accurate. Comparing two operating points with the same counter is reasonable; comparing the counter’s absolute value against an external meter is not.

Temperature is the third variable. A measurement taken on a cold part understates the energy at the operating point, because leakage rises as the part warms and the part will warm during any sustained run. An energy comparison that does not state the junction temperature at which it was made is not reproducible, which is why thermal state belongs in any report of energy per operation.

The design implication

The energy-optimal point is not a fixed voltage. It moves with temperature, with the workload’s memory intensity, with the process corner, and with the age of the part. A design that hard-codes a single “efficient” state will be wrong for most of its life, and a design that tracks the optimum must measure something, which brings back the accuracy problem.

The tractable compromise is a table of states characterised across the expected range, with a governor that selects among them using utilisation and temperature, and a margin that covers the characterisation’s uncertainty. The margin costs energy, and its size is a decision about how much of the theoretical optimum is worth pursuing given the cost of getting it wrong.