Thermal Throttling: Duty Cycles, Ratio Capping, and Power Limits

A processor has several independent reasons to slow itself down, and they are implemented by different mechanisms with different time constants and different observable effects. Treating them as one thing called throttling makes the behaviour look arbitrary: the clock falls at a temperature that does not match the thermal specification, the frequency oscillates between two values under a steady load, or a machine that is cool to the touch still runs at reduced speed. Each of those is a different limiter doing its job.

The limiters fall into two families. Thermal limiters respond to temperature and act on frequency. Power limiters respond to an energy budget over a time window and act on frequency, voltage, and sometimes on the turbo ratio directly. Both ultimately reduce the same quantity, but they are triggered by different sensors and they enforce different constraints.

The thermal monitor and its two responses

Every core has one or more digital thermal sensors, usually a diode-connected transistor biased at a fixed current, whose forward voltage falls predictably with temperature. The reading is compared against a trip point, and crossing it activates the thermal monitor.

The older response is a duty cycle: the processor stops its clock for a fraction of each period, so the effective frequency falls while the voltage stays the same. The duty ratio is set by a control signal, historically a pin the platform could drive and later an internal register. Because the clock is stopped rather than slowed, the average frequency is the nominal frequency multiplied by the duty ratio, and the transition is fast because no phase-locked loop is involved.

The newer and now usual response is ratio capping: the processor reduces its frequency multiplier below the requested turbo ratio, which requires the voltage to fall with it and therefore involves the voltage regulator. This is slower to take effect, on the order of microseconds to milliseconds, because the regulator’s loop and the PLL must settle. The advantage is efficiency: reducing voltage as well as frequency reduces power much more than duty cycling at fixed voltage, so the same thermal relief costs less performance.

The trip point is not the maximum junction temperature. It sits below it, with a hysteresis band, and the difference is the margin that keeps the loop from oscillating around a single threshold. When a core is above the trip point the ratio falls; when it falls back below the lower threshold the ratio recovers. The recovery is usually slower than the reduction, deliberately, because a fast recovery would produce a limit cycle.

The offset between the trip point and the maximum temperature is programmable on many parts, which is why the same silicon can be configured for a quiet system, a performance system, or a fanless system with different thermal behaviour and no hardware change. The offset sets how far below the maximum temperature the trip point sits, and the setting is a platform decision that is usually locked by firmware.

Power limiting is a different constraint entirely

A power limit says that the average power over a window must not exceed a value. It is enforced by a controller that accumulates an estimate of energy consumed, compares it against the budget for the elapsed window, and adjusts the frequency to keep the average on target.

The estimate comes from on-die energy counters that model the power of each domain from activity and voltage, rather than from a current measurement. The model is calibrated per part and is accurate enough to enforce a budget but not accurate enough to be a measurement instrument, which matters when comparing two parts or two workloads.

Two limits are typically configured: a sustained limit enforced over a long window and a short-term limit that allows a burst above the sustained value for a limited time. The long window is on the order of the thermal time constant of the package and heat sink, because the purpose of the sustained limit is to protect the thermal solution rather than the die; the short window is on the order of milliseconds, because its purpose is to allow the part to use the thermal capacitance of the die and spreader for brief bursts.

The interaction with temperature is what produces the familiar behaviour of a laptop or a small form-factor machine: a workload starts at a high turbo ratio, holds it for the duration of the short window, then drops to the sustained ratio, and the drop is a step rather than a gradual decline. If the cooling system cannot remove the sustained power, the temperature continues to rise and the thermal limiter takes over on top of the power limiter, producing a second, slower decline.

A third limit protects the voltage regulator. If the regulator’s current or temperature exceeds its rating, it asserts a signal that forces the processor to reduce its ratio, independently of the die’s own temperature. This is the limiter that fires when a machine is cool but the power delivery components are hot, and it is often the binding constraint in a thin chassis with poor airflow over the regulator.

What the limiters do to the workload

The observable effect is not a uniform slowdown. A frequency cap changes the ratio between compute time and memory time, because the memory clock is usually unaffected. A workload that is compute-bound slows in proportion to the ratio; one that is memory-bound slows much less, because its time is dominated by latency that does not change. A workload with a mixture changes its balance, and its performance per watt can improve as the ratio falls even though its wall-clock time worsens, because the delivery chain loses a smaller share of a lower current at a lower voltage.

That is the basis for the standard optimisation: running at the lowest ratio that still meets a deadline uses less energy than running faster and idling. The relationship is not linear because voltage scales with frequency, so the energy per operation falls faster than the time per operation rises, up to the point where leakage and fixed costs dominate. The arithmetic of that optimum is the subject of energy-optimal operating points.

Throttling also interacts with timing measurement. A benchmark that assumes a constant frequency will misattribute the slowdown: the same instruction sequence takes longer, and the counter values that measure cycles may or may not scale with the ratio depending on whether the counter runs on the core clock or a fixed reference. Tools that report a “effective frequency” derive it from a fixed-reference cycle counter divided by elapsed time, which gives the average ratio over the interval rather than the instantaneous one.

The control loop, and why it can oscillate

Both limiters are feedback loops with delay. The thermal loop’s delay is the sensor’s response time, the die’s thermal time constant, and the regulator’s settling time, which together can be tens of milliseconds. A loop with that much delay and a proportional response will oscillate unless the gain is small, so the controller is deliberately slow: it moves the ratio in small steps and waits.

The power loop’s delay is shorter but it has its own instability. A window-based controller that integrates energy over a window and corrects at the end of each window produces a sawtooth: the part runs above the budget early in the window and below it late, and the average is correct while the instantaneous power is not. Shortening the window reduces the excursion but makes the controller react to bursts that the thermal capacitance would have absorbed, which wastes performance.

The visible symptom of a badly tuned loop is a periodic variation in frame rate or throughput at a frequency of a few hertz, with no corresponding change in the workload. It is distinguishable from thermal throttling by its regularity and by the fact that it persists even when the part is well below its temperature limit.

Sensors, calibration, and the limits of the model

A digital thermal sensor reports a value relative to a per-part offset that is programmed during manufacturing test. The offset compensates for process variation in the sensor’s own characteristic, and it is why two parts with the same reading are at the same temperature even though their sensors differ. A part whose offset was miscalibrated will throttle at the wrong temperature, which is a manufacturing escape rather than a design error.

The sensor’s location is a further approximation. It sits at one point on the die, chosen to be representative of the hottest sustained region, but the actual hot spot moves with the workload and can be several kelvin above the sensor. The thermal specification accounts for this with a margin, and the margin is why the trip point is below the maximum junction temperature rather than equal to it.

The power model has a similar issue. Its activity counters see switching, not current, so a workload that draws high current at low activity, such as a dense vector operation on a small fraction of the die, is underestimated by a model tuned for average activity. Designs add a current-aware term for the high-power domains, and the residual error is covered by the sustained limit’s margin.

When throttling is the design, not the fallback

For a fanless device, the thermal limiter is part of the product. The part is allowed to reach its trip point under sustained load and to settle at whatever ratio the passive cooling supports, and the specification quotes that settled ratio rather than a peak. The same is true of a thin laptop: the sustained ratio after the burst window is the number that matters to a user, and the peak turbo ratio is a transient that lasts seconds.

Designing for that means sizing the thermal solution for the sustained power, not the peak, and ensuring the transient behaviour is acceptable: the ratio must not drop so far that interactive latency becomes visible, and the fan, if there is one, must not ramp audibly in response to every burst. The control loop’s parameters, not just the cooling hardware, decide whether the product feels consistent.