Return Current Paths and Why Loop Area Sets Trace Inductance

A driver pushes a voltage onto a trace, and the receiver on the other end compares that voltage to its own local reference. Between the two devices there must therefore be a complete circuit: current leaves the driver, travels the trace, enters the receiver, and comes back. The trace is only half of that circuit. The other half runs through whatever conductor the designer forgot to think about, and its geometry, not the trace’s, is usually what determines whether the board works.

A signal is a loop, not a wire

At the instant a driver switches, the voltage step propagates down the trace as an electromagnetic wave guided by the trace and the conductor beneath it. The associated current is not a stream of electrons injected at one end and drained at the other; it is a displacement current between the trace and the reference conductor, with a conduction current in each. The trace carries current in one direction, the reference plane carries an equal current in the opposite direction, and the two are separated by the dielectric.

Because the two currents are equal and opposite and separated by a distance, they form a loop with an area. That area is what the signal sees as inductance. The relation is the one every first circuits course gives for a loop: flux through the enclosed area per unit current, with the loop inductance roughly proportional to the area and inversely proportional to the conductor width. A trace 0.15 mm wide sitting 0.1 mm above a plane encloses very little area per millimetre of length and has a partial self-inductance of a few tenths of a nanohenry per millimetre. The same conductor in free space, with its return somewhere indeterminate, is closer to 1 nH per millimetre, the textbook figure for an isolated wire.

That difference of a factor of two or three is not a curiosity. Inductance converts a changing current into a voltage, $V = L , di/dt$, and one nanohenry carrying one ampere per nanosecond develops exactly one volt. Modern logic edges routinely change tens of milliamps in a few hundred picoseconds, so a fraction of a nanohenry of unwanted path is already tens of millivolts of noise appearing where the receiver expects a quiet reference.

Where the return current actually flows

The path the return current takes is chosen by the same rule that governs any parallel network: it divides inversely with impedance. At DC and at low frequency, resistance dominates, and the current spreads through the reference plane along the geometrically shortest low-resistance route, which may be nowhere near the trace. As frequency rises, inductive reactance $2\pi f L$ grows with $f$ while resistance stays fixed, and the current redistributes to minimise loop inductance instead. Above a few hundred kilohertz on a typical board, the return current has already migrated to the region directly beneath the trace.

The distribution is not a thin filament. Current density under a microstrip peaks on the plane surface directly below the trace centre and falls off laterally, and it also decays with depth into the copper because of the skin effect. At 100 MHz the skin depth in copper is about 6.6 µm; at 1 GHz it is about 2 µm. One-ounce copper is roughly 35 µm thick, so at high frequency only the top few micrometres of the plane carry the return, which is why surface finish and roughness matter on high-speed planes and why a plane with a slot milled into it is electrically absent even though copper remains on both sides.

A useful mental model: the return current is lazy and wants to stay as close to the signal as possible, and it spreads sideways only as far as it must to find copper. A plane is not a zero-impedance node. It is a distributed conductor with its own inductance, resistance, and potential differences across it.

What a broken return path costs

Crossing a plane split

Placing two ground nets on one layer with a gap between them is common: analog and digital grounds, or a quiet plane and a connector plane. Any trace routed across that gap loses its reference for the width of the gap. The return current cannot jump the slot; it must detour around the end of the slot, and the detour length can be tens of millimetres.

The consequences compound. The loop area for that section of trace grows by the detour, so the local inductance rises sharply and the trace’s impedance is no longer the value the layout was designed for, producing a reflection at the crossing. The enlarged loop also radiates: a loop antenna’s efficiency rises with area, and the slot itself behaves as a resonant structure with the plane around it. Common-mode current is induced on cables attached to the board, which is the usual mechanism by which a board fails an emissions test at a frequency no clock on it generates.

The practical rule is absolute for high-speed nets: never route across a split, and if a net must cross, provide a stitching capacitor or a bridge of vias joining the two planes at the crossing point so the return current has a short path. A stitching capacitor is a compromise, because its own mounting inductance appears in series with the return path; the correct fix is not to split the plane in the first place, or to keep the split away from every fast net.

Changing reference layers

A signal that moves from a layer referenced to the ground plane to a layer referenced to a power plane changes which conductor carries its return. The return current must transfer from the ground plane to the power plane at the point of the layer change, and it can only do so where the two planes are connected — through a decoupling capacitor or a ground via.

If the nearest such connection is far away, the return current takes a long detour through the power distribution network, and the via transition becomes a large discontinuity. The standard layout answer is a return via placed within a millimetre or two of the signal via, so that the return path changes layers through a short, low-inductance connection. On boards with many layer-changing differential pairs, the return vias are placed as a group beside the signal vias and the planes are stitched around the group.

Returns in connectors and packages

The same argument applies wherever the signal leaves the board. A connector that provides one ground pin per eight signal pins forces the return current of eight signals through one pin’s inductance. For a ribbon cable, the classic arrangement alternates signal and ground conductors, which gives every signal an adjacent return and reduces the effective loop to the pitch of the cable. For a high-density board-to-board connector, the manufacturer’s pin assignment for high-speed groups already reflects this; re-assigning pins to make routing easier routinely destroys the return path the connector was designed to provide.

Inside a package the effect is stronger because the distances are smaller but the currents are larger. A ball grid array with a single ground ball shared by several high-speed outputs develops a common impedance that couples every output into every other one. Package substrate design treats ground balls as a resource allocated per signal group, and the board’s via fanout must preserve that allocation rather than funnel several signals’ returns through one via. The same shared-impedance path is what makes a plane’s own impedance a design quantity, which is where Power Delivery Network Impedance and the Target It Must Hold takes up the argument for the supply side.

Sizing the effect

Two numbers make the mechanism concrete. The first is the loop inductance of the detour; the second is the voltage it produces for a given edge rate.

def bounce_volts(inductance_nh, di_over_dt_a_per_ns):
    # 1 nH carrying 1 A/ns develops exactly 1 V: nH * A/ns == V
    return inductance_nh * di_over_dt_a_per_ns

# Return current detoured 20 mm around the end of a plane slot instead of
# running directly beneath the trace. A wide plane path is roughly 0.3 nH/mm,
# against about 0.2 nH/mm for the direct path under a 0.1 mm dielectric.
detour_nh = 20 * 0.3
print(f"{detour_nh:.1f} nH of added path")
print(bounce_volts(detour_nh, 0.05))  # volts, for a 50 mA/ns edge
print(bounce_volts(detour_nh, 0.2))   # a faster edge through the same detour

The numbers are order-of-magnitude, but the structure of the result is what matters: the penalty is linear in detour length and linear in edge rate, so a layout that is acceptable for a slow edge becomes unacceptable when the same net is re-clocked faster. Nothing about the trace changed, and no amount of termination at the ends removes the disturbance, because it is generated in the middle of the route.

Where the rule stops applying

The “return current flows beneath the trace” model assumes the reference conductor is wide compared with the trace height and is continuous. It degrades when the plane is narrow, when the trace is far above the plane relative to its width, and when the frequency is low enough that resistance still dominates. Slow, low-current nets — a status LED, a relay drive, a reset line held for milliseconds — genuinely do not care, and treating every net on the board as a transmission line produces unusable layouts.

The boundary is set by edge rate rather than clock frequency, and it is taken up in Rise Time, Electrical Length, and When a Trace Stops Being a Wire. The return path is the first thing to establish on any net that crosses that boundary, because every later decision — termination, stackup, via placement — assumes it holds.