Characteristic Impedance from Stackup Geometry

A controlled-impedance board is one where the fabricator is told a target impedance for specified layers and guarantees it within a tolerance, typically ±10%. The number is not a property of the copper alone. It is a property of the cross-section: the width of the trace, the thickness and permittivity of the dielectric beneath it, the thickness of the copper itself, and — for a trace on an outer layer — the presence of air above and solder mask on top. Change any of them and the impedance changes, which is why a design that is impedance-controlled must fix its stackup before routing begins.

The distributed model behind the number

A uniform trace above a plane has, per unit length, a series inductance and a shunt capacitance to the reference. In the lossless limit the characteristic impedance is

$$Z_0 = \sqrt{\frac{L}{C}}$$

and the velocity is $1/\sqrt{LC}$. The two equations together mean that $Z_0$ and propagation delay are not independent: for a fixed dielectric, lowering the impedance by making the trace wider raises $C$ per unit length and lowers $L$, and the product $LC$ stays tied to the dielectric.

That is the reason impedance and delay can both be predicted from geometry. It is also the reason a narrow trace and a wide trace of the same length on the same layer arrive at the same time even though their impedances differ. Delay is set by the material; impedance is set by the shape.

The useful rearrangement is that $Z_0$ falls as capacitance per unit length rises. A wide trace close to its plane has high capacitance and low impedance; a narrow trace far from its plane has little capacitance and high impedance. Everything else in stackup design is a refinement of that trade.

Two cross-sections and their equations

Stripline

A stripline is a trace centred between two reference planes. The field is entirely in the dielectric, so the medium is homogeneous and the effective permittivity is simply $\varepsilon_r$. The IPC-2141A approximation for a zero-thickness trace is

$$Z_0 \approx \frac{60}{\sqrt{\varepsilon_r}} \ln!\left(\frac{4b}{0.67\pi w}\right)$$

where $b$ is the total plane-to-plane spacing and $w$ is the trace width. The copper thickness enters through a correction that replaces $w$ with an effective width, and for one-ounce copper (about 35 µm) the correction is small for wide traces and significant below roughly 0.15 mm.

Two features of the stripline matter in practice. Because the field is symmetric, the return current splits between the two planes in proportion to the distances; a trace placed off-centre puts more return current in the nearer plane. And because both sides are laminate, the impedance does not depend on solder mask, plating, or air, which makes stripline the more predictable of the two structures and the reason critical nets are often moved to inner layers.

Microstrip

A microstrip is a trace on an outer layer with dielectric below and air above. The field is partly in each, so the effective permittivity is an intermediate value that depends on geometry. The IPC-2141A approximation is

$$Z_0 \approx \frac{87}{\sqrt{\varepsilon_r + 1.41}} \ln!\left(\frac{5.98h}{0.8w + t}\right)$$

with $h$ the dielectric height and $t$ the copper thickness. The presence of air raises the impedance for a given geometry compared with what the same width would give if fully embedded, because air contributes capacitance-free volume. The price is that the field is exposed, which makes the microstrip more sensitive to the environment: a solder-mask coating, a conformal coat, a finger, or a nearby enclosure all perturb it.

Both formulas are curve fits to field-solver results and are quoted with an accuracy of a few percent over a limited range of $w/h$. They are useful for sanity checks and for choosing a starting width. They are not a substitute for the fabricator’s field solver, which is what actually produces the impedance table used to build the board.

Working an example

Take a four-layer board with a 0.1 mm dielectric between the top layer and the first inner plane, and a target of 50 Ω on the microstrip layer with $\varepsilon_r = 4.3$ and 35 µm copper. Solving the microstrip relation for width gives about 0.145 mm, a little under 6 mil. The same target on a 0.2 mm dielectric needs a trace over 0.3 mm wide, which is the reason thin dielectrics are what make dense high-speed routing possible at all: they let a narrow trace reach 50 Ω.

import math

def microstrip_z0(w_mm, h_mm, er, t_mm=0.035):
    return 87 / math.sqrt(er + 1.41) * math.log(5.98 * h_mm / (0.8 * w_mm + t_mm))

def stripline_z0(w_mm, b_mm, er):
    return 60 / math.sqrt(er) * math.log(4 * b_mm / (0.67 * math.pi * w_mm))

# 50 ohm microstrip on 0.1 mm prepreg, er 4.3
for w in (0.10, 0.125, 0.14, 0.15, 0.20):
    print(f"w={w:.3f} mm  Z0={microstrip_z0(w, 0.1, 4.3):.1f} ohm")

# same width as stripline in a 0.4 mm cavity: a different width reaches 50 ohm
print(f"stripline 0.135 mm in 0.4 mm: {stripline_z0(0.135, 0.4, 4.3):.1f} ohm")

The sensitivity is the important output. Near 0.14 mm, a 0.02 mm change in width moves the microstrip impedance by several ohms, and a 0.01 mm change in dielectric height moves it by about the same amount. Etch tolerance on an outer layer is commonly ±0.02 mm or worse, and prepreg thickness varies with the copper balance of the layers it covers, so the fabricator’s ±10% window is not generous — it is close to the limit of what the process can hold without special measures.

The stripline comparison is the second output worth reading, and it needs care because the two geometries are not the same height. A 0.4 mm cavity with the trace centred puts 0.2 mm of dielectric on each side, twice the microstrip’s 0.1 mm, yet the width that reaches 50 Ω is about the same, 0.135 mm against 0.145 mm. The buried trace has dielectric on both faces rather than air on one, so it carries more capacitance per unit width for a given height; doubling the height and filling the top half with laminate roughly cancel. Change the layer without changing the stackup height and the impedance moves by tens of percent, which is why the fabricator’s impedance table is per layer rather than per board.

Differential pairs are two coupled lines

A differential pair is not two independent 50 Ω traces. Each conductor’s field overlaps the other’s, so the pair has two modes. In the odd mode — the one excited by a differential signal — the currents are equal and opposite, the voltages are opposite, and the mutual capacitance and mutual inductance both act to lower the impedance seen by each line. The odd-mode impedance $Z_{odd}$ is therefore below the uncoupled single-ended value, and the differential impedance is $2 Z_{odd}$.

The even mode, where both conductors carry the same signal, leaves the mutual capacitance uncharged because there is no voltage between the conductors; each line then sees less effective capacitance than it would alone, and the mutual inductance adds to the series flux, so $Z_{even}$ is higher than the single-ended value. A pair that is not symmetric — one line closer to a plane, or one line wider after etch — converts part of a differential signal into a common-mode component, which then radiates from the pair as if it were a single wire.

Coupling strength depends on the gap. Widening the gap raises $Z_{odd}$ toward the uncoupled value and reduces the differential impedance’s sensitivity to the gap, at the cost of board area and of the pair’s immunity to nearby aggressors. Most designs settle on a gap comparable to the trace width, which gives a differential impedance around 85 to 100 Ω for a pair whose single-ended lines are near 50 Ω.

The practical consequence for layout is that the pair must maintain its gap as carefully as its width. A pair that splits around a via or a keep-out changes its differential impedance locally, and the resulting common-mode component appears at the receiver as a differential offset and at the enclosure as emission. The symmetry argument is developed further in Differential Pairs and the Cost of Asymmetry.

Why a layer change breaks the number

Every geometry above assumes the trace stays on one layer at one height above one plane. A via violates all three assumptions at once: the trace leaves the layer, passes through a barrel whose diameter is larger than the trace width, and arrives at a different height above a different plane.

The via barrel presents a local capacitance to every plane it passes through, and the antipad — the clearance around the barrel — removes copper from those planes. The combination is a short section of low impedance followed by a section of high impedance, which reflects part of the incident wave. On a 50 Ω net the discontinuity is small enough to ignore below a few hundred picoseconds of edge; above that it becomes one of the dominant sources of jitter and eye closure. Back-drilling the unused portion of the barrel, and choosing a via whose antipad is sized rather than defaulted, are the standard mitigations, and both are treated in Via Transitions, Stubs, and Backdrilling.

The design rule that follows is that the stackup must be planned so that a net’s critical sections stay on one layer as far as possible. When a layer change is unavoidable, the impedance target should be re-checked for the new layer rather than assumed to carry over.

What the tolerance really means

A fabricator’s ±10% guarantee is a guarantee about the cross-section it builds, measured on a test coupon, not about every trace on the board. Within a panel, dielectric height varies with the copper distribution of the layers above and below; near the panel edge, etch behaves differently; and plating thickness on outer layers varies with the current distribution during plating.

For a 50 Ω target, ±10% is 45 to 55 Ω. A receiver designed for a 50 Ω source sees a reflection coefficient of about ±0.05 at that boundary, which is a few percent of the incident amplitude — small enough that most single-ended interfaces tolerate it. High-speed serial links with tighter loss budgets often specify ±7% or better and require the fabricator to demonstrate it on coupons from the same panel. The tighter number is bought with controlled etch compensation and a stackup that uses the same prepreg build everywhere, and it is one of the reasons high-layer-count boards cost what they do.