Rise Time, Electrical Length, and When a Trace Stops Being a Wire

A wire is a simplification. It holds only while the voltage along it is approximately the same at every point, which is true when the signal has had time to settle everywhere before it is measured. A driver that changes its output in a nanosecond does not give the trace that time: the change arrives at the far end a measurable interval later, and during that interval the two ends of the trace are at different voltages and carry different currents. The trace is then a distributed structure, and the rules that apply to it are the rules of transmission lines.

Delay comes from the dielectric, not the copper

The speed at which a step propagates along a trace is set almost entirely by the insulating material around it. In a homogeneous medium the velocity is

$$v = \frac{c}{\sqrt{\varepsilon_r}}$$

where $c$ is the speed of light in vacuum, about $3 \times 10^8$ m/s, and $\varepsilon_r$ is the relative permittivity of the dielectric. The copper only guides the wave; its conductivity affects loss, not velocity.

For a stripline — a trace buried between two planes, fully surrounded by dielectric — the medium is homogeneous and the formula applies directly. FR-4 laminate has a relative permittivity around 4.2 to 4.5 at low frequency, so the velocity is roughly half the speed of light and the propagation delay is about 6.5 to 7 ps per millimetre, or 165 to 180 ps per inch. For a microstrip — a trace on an outer layer with dielectric below and air above — the field splits between two media, and the effective permittivity $\varepsilon_{eff}$ lies between 1 and $\varepsilon_r$, closer to $\varepsilon_r$ for a wide trace and closer to 1 for a narrow one. The result is a slightly faster wave, around 6.0 to 6.2 ps/mm for typical geometries, and a mild dependence of impedance and delay on trace width that buried traces do not have.

Two practical consequences follow. First, delay is a property of the stackup and the layer, so two traces of the same length on a microstrip layer and a stripline layer are not the same length in time. Second, $\varepsilon_r$ is not constant: it falls slowly with frequency in laminate materials, which is one component of the dispersion that spreads a fast edge as it travels.

The quarter-wave criterion and its practical form

The formal condition for treating a connection as a lumped element is that its physical extent be small compared with the wavelength of the highest frequency present. A common threshold is one-sixth of a wavelength, at which the phase shift along the structure is about 60 degrees and the voltage variation along it is no longer negligible.

The highest frequency in a digital edge is not the clock frequency. A step with a 10–90% rise time $t_r$ has a spectral envelope that stays roughly flat up to a knee frequency near $f_{knee} \approx 0.35 / t_r$ and then rolls off. Layout rules usually state the criterion in a form that skips the wavelength entirely: a trace must be treated as a transmission line when its one-way delay exceeds about one-sixth of the rise time. The two forms are not numerically the same — the wavelength test applied at the knee is the looser of the two — which is why the rise-time version is the one that gets applied.

$$\text{critical length} \approx \frac{t_r}{6} \cdot v$$

With a 1 ns rise time and the 6.5 ps/mm stripline velocity, the critical length is about 25 mm. With a 300 ps rise time, it is about 8 mm. A 200 MHz clock in a modern CMOS process may well have a 300 ps edge, which is why clock frequency is a poor guide: a 50 MHz signal generated by a fast buffer with a 500 ps edge already needs transmission-line treatment on a 15 mm route.

The criterion is a guideline rather than a boundary. Below it, reflections still exist; they are merely small enough that the overshoot and settling they cause stay inside the receiver’s margin. Above it, treating the trace as a wire produces predictions that are wrong by a large factor.

What the far end sees before termination

Consider a driver with output resistance $R_S$ launching a step into a line of characteristic impedance $Z_0$, terminated by a receiver of high impedance. The incident wave has amplitude $V_{step} \cdot Z_0/(Z_0 + R_S)$ and travels at velocity $v$. Until it arrives, the receiver sees the old level and the driver sees only the line.

At the open end the reflection coefficient is $+1$, so the arriving wave doubles: the receiver voltage jumps to twice the incident amplitude, then a reflected wave travels back. At the source the reflection coefficient is $(R_S - Z_0)/(R_S + Z_0)$, which is negative for a typical driver, so the returning wave is inverted and partially re-launched. The result is a staircase of reflections bouncing between the two ends, each step smaller, converging on the final DC level.

Three observable effects come out of this. The first is overshoot at the receiver: with a source impedance much lower than $Z_0$ and no termination, the first arrival can approach twice the intended amplitude, which forward-biases input protection diodes and, on a bus, couples into neighbouring nets. The second is ringing at a period of twice the line delay, which is exactly the frequency at which the structure resonates. The third is a settling tail: the time to reach the final level within a tolerance band is longer than the edge itself, and it scales with the reflection coefficient magnitude.

The same analysis applies to a driver whose impedance happens to match the line. In that case the source reflection coefficient is zero, the first incident wave is half the step, the doubling at the open end produces exactly the intended level, and no further reflections occur. That is series termination, and it is why a series resistor at the driver is the cheapest fix for a point-to-point net.

Why a slow edge on a long trace is still a problem

The rise-time criterion tempts a conclusion that is wrong in a specific case. If the edge is slow compared with the line delay, the first incident wave is still travelling while the driver is still changing, and the reflections overlap and largely cancel. Overshoot disappears. What does not disappear is the total delay and the settling behaviour.

A long unterminated line driven by a slow edge behaves as a capacitor being charged through the line’s distributed inductance, and the receiver’s threshold crossing can occur later than the nominal time-of-flight predicts. In a bus where several loads hang off the same trace, the reflections from each load add, and a slow edge that looks clean at one load can produce a non-monotonic transition at another. A non-monotonic edge is a real hazard on clock and strobe nets: a receiver that sees the level cross its threshold, fall back, and cross again can capture two edges from one transition.

There is also the case where the edge is fast but the trace is short, and the load is large. A short trace with several receivers presents a capacitance comparable to the trace’s own; the line’s effective impedance falls and the delay rises. The lumped approximation still applies if the loads are spaced closer than the critical length, which is the basis for treating a memory bus with closely spaced devices as a single distributed load rather than as a set of separate stubs.

Choosing the model

The decision is made per net, from three inputs: the rise time of the fastest driver that can reach the net, the one-way delay of the route, and the impedance of the load.

PS_PER_MM = 6.5                  # stripline in FR-4, er ~4.3

def model_for(length_mm, rise_ps, loads=1):
    delay_ps = length_mm * PS_PER_MM
    ratio = delay_ps / rise_ps
    if ratio < 1 / 6:
        return "lumped", delay_ps
    if loads > 1 and delay_ps < rise_ps:
        return "distributed load, lumped per segment", delay_ps
    return "transmission line", delay_ps

print(model_for(10, 1000))   # short and slow: a wire is adequate
print(model_for(60, 300))    # 390 ps of delay against a 300 ps edge

The third branch is where termination, stackup impedance control, and return-path discipline start to matter. The reflection staircase just described is what the resistor networks in Termination Topologies and the Reflection They Absorb exist to suppress, and the choice of where to place the resistor follows from which end of the line is allowed to reflect. Below the threshold, the same nets still benefit from a continuous reference plane, because the return current argument in Return Current Paths and Why Loop Area Sets Trace Inductance applies at every frequency where the return current has begun to crowd. What changes above the threshold is that the trace’s impedance becomes a number the design must control, which is the subject of Characteristic Impedance from Stackup Geometry.

Where the criterion misleads

The one-sixth rule uses the rise time at the driver. It ignores the receiver’s input capacitance, which slows the arriving edge and, for a large load, changes the effective rise time at the point where it matters. It also ignores losses: on a long line the dielectric and copper loss round the edge further, so a route that the geometric criterion calls marginal may behave well, while a route that the criterion calls comfortable may show inter-symbol interference at high data rates.

The criterion also assumes a single, uniform cross-section. A trace that changes layer, passes a connector, or crosses a plane boundary has discontinuities that behave as lumped elements regardless of total length. Those are covered in Via Transitions, Stubs, and Backdrilling, and they are the reason a short route can still fail where a long uniform one succeeds.