Tag
timing
- Jun 25, 2026 Mercury Delay-Line Memory and the Timing It Imposed How acoustic pulses recirculating in mercury hold a bit stream, why access time depends on the address, and what that forced on instruction placement and memory layout. computing history
- Mar 30, 2026 Measurement Overhead and the Code the Compiler Deletes How dead-code elimination, loop unrolling, and constant folding silently remove the work a benchmark claims to time, and which structural defences keep the timed region intact. performance engineering
- Nov 11, 2025 Carry Propagation in the Difference Engine No. 2 How a figure wheel registers that a carry is owed without performing it, how the latched warnings are serviced by staggered carry arms, and what the two-phase cycle costs in timing. computing history
- Oct 30, 2025 Combinational Hazards and Why Consensus Terms Eliminate Glitches How unequal path delays produce output pulses in a logically correct circuit, how static and dynamic hazards differ, and when adding redundant logic is the fix. hardware engineering
- May 5, 2025 Clock Networks, Global Buffers, and Skew Budgets Why a clock reaches every register through a dedicated balanced tree, what skew and jitter cost a timing budget, and when a clock must be routed on general interconnect instead. hardware engineering
- Feb 22, 2025 Warmup Transients and Detecting Steady State in Timed Loops Why the first iterations of a timed loop measure a different program, which subsystems are still converging, and how to locate the transition into steady state rather than assuming it. performance engineering
- Nov 12, 2024 Clock Sources and the Resolution Floor of a Timing Call How monotonic clocks, TSC reads, and syscall-based time differ in cost and granularity, why a measured interval is a difference of two uncertain readings, and how the floor limits what a benchmark can resolve. performance engineering
- Oct 5, 2024 Setup and Hold Time, Metastability, and the Two-Flop Synchronizer Why a flip-flop needs its input stable around the clock edge, how a near-threshold sample resolves probabilistically, and how cascaded flops bound the failure rate. hardware engineering
- Aug 18, 2024 Switch Access and Row-Column Scanning How a single switch lets a user navigate every control on screen through timed scanning, and how the scan timing and group layout determine entry speed. accessibility
- Jul 27, 2022 Scheduling Without a Scheduler: Superloops and Their Latency Budget How a main loop plus interrupt handlers bounds worst-case response time, where jitter creeps in, and the point at which the structure stops meeting its deadlines. embedded systems
- Mar 11, 2022 Cue Timing in Captions and the Problem of Describing What Is Not Said How WebVTT cues are placed in time and space, what reading-rate limits imply about line length, and why audio description has to fit into gaps that the mix does not leave. accessibility