Computer Architecture · Cluster
Instruction Sets
Encoding, addressing modes, and ISA families.
- 01 Fixed-Width Instruction Encoding and Where the Fields Go How a 32-bit instruction divides into opcode, register and immediate fields, why the register fields keep the same bit offsets across formats, and what that costs in reachable constants.
- 02 Addressing Modes and How an Effective Address Is Computed How base, index, scale and displacement fields combine into an address, why some ISAs fold memory operands into arithmetic, and what each mode costs in the datapath.
- 03 Opcode Space Allocation and How Extensions Claim Encodings How an instruction set divides its opcode map among base operations, extensions and vendor additions, and what happens when the map runs out of room.
- 04 Register Windows and Why Explicit Operand Registers Won How register window architectures eliminate spill code on call, what the window management traps cost, and why load-store ISAs settled on flat register files with fixed fields.
- 05 Immediate Encoding and How Arbitrary Constants Get Materialized Why an instruction can hold only a small constant, how sign extension and scaled fields are packed into the word, and the instruction sequences that build a full-width value.
- 06 Condition Codes, Flag Registers and the Dependency They Create How comparison results become flags, why an implicit flag register serialises code, and how architectures that compare directly into registers avoid the hazard.
- 07 Two-Operand Encodings and the Destructive Write Problem Why the second source register disappears in a two-operand format, how destructive writes constrain register allocation, and what a three-operand format buys back.
- 08 SIMD Encoding: Vector Register Fields, Predication and Length How vector instructions spend their encoding bits on register numbers, masks and element widths, and why vector length is sometimes in the instruction and sometimes in a control register.
- 09 Decode Bandwidth and the Cost of Variable Instruction Length Why fixed-width instructions let a front end decode several per cycle, how variable-length encodings force serial scanning, and where the two approaches land on fetch and decode throughput.
- 10 ISA Families, Extension Levels and Binary Compatibility How architectures partition optional instructions into named levels, how a binary discovers what the current processor implements, and where forward compatibility quietly breaks.