Topic domain
Computer Architecture
How processors turn instructions into work.
- Articles
- 80
- Clusters
- 8
- Foundational
- 24
- Intermediate
- 32
- Advanced
- 24
Encoding, addressing modes, and ISA families.
- Fixed-Width Instruction Encoding and Where the Fields Go
- Addressing Modes and How an Effective Address Is Computed
- Opcode Space Allocation and How Extensions Claim Encodings
- Register Windows and Why Explicit Operand Registers Won
- Immediate Encoding and How Arbitrary Constants Get Materialized
- Condition Codes, Flag Registers and the Dependency They Create
Pipelining
10Hazards, forwarding, and deep pipelines.
- The Five-Stage Pipeline and the Throughput It Buys
- Forwarding Paths and the Load-Use Stall That Survives Them
- Structural Hazards and the Cost of Duplicated Resources
- Control Hazards: What a Branch Costs Before It Resolves
- Interlocks, Bubbles, and How a Stall Propagates Backwards
- Delay Slots and the Burden They Move to the Compiler
Renaming, scheduling, and retirement.
- Why an In-Order Pipeline Stalls and What an Instruction Window Buys
- Register Renaming and the Elimination of False Dependencies
- The Reorder Buffer and In-Order Retirement
- Issue Queue Wakeup and Select: The Scheduler Inside the Window
- Load-Store Ordering and Memory Disambiguation in a Speculative Machine
- Checkpointing and Recovery from Misprediction
Speculation, misprediction cost, and recovery.
- The Control Hazard and Why Fetch Must Guess the Next Instruction
- Static Branch Prediction and the Branch Delay Slot
- Two-Bit Saturating Counters and the Bimodal Predictor
- How a Branch Target Buffer Delivers the Target in the Fetch Cycle
- Global History and the Gshare Index
- Misprediction Recovery: Checkpoints, Squash, and the Cost of Being Wrong
Wide issue and data-parallel execution.
- Issue Width and the Structural Ceiling on Instructions per Cycle
- VLIW Bundles and the Compiler as Scheduler
- Fixed-Width SIMD Lanes Versus Scalable Vector Registers
- Register File Ports and Operand Delivery
- Software Pipelining and Loop-Carried Dependences
- Vector Chaining and What It Costs in the Register File
Ordering rules and fence semantics.
- Sequential Consistency and the Cost of One Global Memory Order
- Cache Coherence Is Per Location, Consistency Is Not
- Store Buffers and the Total Store Order That Replaces Sequential Consistency
- Acquire and Release as One-Way Ordering Constraints
- What a Fence Instruction Actually Does to the Pipeline
- Litmus Tests and How Allowed Outcomes Are Decided
Accelerators
10Specialized units and host-device interfaces.
- The Cost of Generality: Why Fixed-Function Logic Wins
- Memory-Mapped Registers and the Ordering Rules Behind a Store
- Descriptor Rings and the Producer-Consumer Contract
- Device DMA and the IOMMU Boundary
- Interrupt Moderation and Event Delivery at High Rates
- Systolic Arrays and Dataflow Scheduling
Power, area, and performance budgets.
- The Power Wall: Why Frequency Scaling Stopped
- The Area Budget: Reticle Limits, Yield, and Cost per Die
- Clock and Power Gating: Computing the Break-Even Point
- Thermal Design Power and the Throttling It Authorises
- Power Density and the Dark Silicon Constraint
- Voltage and Frequency Domains: Why DVFS Is Not One Knob
All Computer Architecture articles
- Oct 22, 2026 Voltage and Frequency Domains: Why DVFS Is Not One Knob How a frequency change requires a voltage change, why level shifters and synchronisers appear at domain boundaries, and what latency an operating-point transition really costs.
- Oct 12, 2026 Issue Queue Wakeup and Select: The Scheduler Inside the Window How a queue of waiting instructions learns that its operands are ready, how one instruction per port is chosen each cycle, and why the broadcast network is the hard part.
- Oct 2, 2026 Propagation, Cumulativity, and Why Weak Models Need Transitive Visibility Messages that preserve ordering are not enough: a store already observed by one thread must be observed by every thread it reaches, and multi-copy atomicity is the property that says so.
- Sep 22, 2026 Thermal Design Power and the Throttling It Authorises What a TDP rating specifies, why a part may exceed it briefly, how the control loop reacts to temperature and current limits, and why two parts with the same TDP perform differently.
- Sep 20, 2026 Acquire and Release as One-Way Ordering Constraints How a release store and an acquire load each constrain ordering in only one direction, and why the pair is enough to publish data without a full fence.
- Sep 10, 2026 Issue Width and Its Diminishing Returns Why widening an out-of-order issue window costs area and energy faster than it buys performance, and where the wakeup, select, and bypass networks set the ceiling.
- Sep 1, 2026 Power Density and the Dark Silicon Constraint Why a chip can contain more transistors than its power budget can switch at once, how that forces area to be specialised, and what fraction of a die can be active at any instant.
- Aug 26, 2026 Read-Modify-Write Atomicity and the Ordering It Carries Why an atomic increment cannot be built from a load and a store, what compare-and-swap costs in coherence traffic, and how an atomic operation acts as a fence.
- Aug 24, 2026 Register Windows and Why Explicit Operand Registers Won How register window architectures eliminate spill code on call, what the window management traps cost, and why load-store ISAs settled on flat register files with fixed fields.
- Jul 24, 2026 Litmus Tests and How Allowed Outcomes Are Decided How a few lines of concurrent code pin down a memory model, how tools enumerate the executions, and why "never observed" is weaker than "forbidden".
- Jul 17, 2026 Compiler Reordering and the Contract It Must Not Break Why an optimiser may sink an atomic load past a store only in certain cases, where the as-if rule stops, and how data races turn a performance model into undefined behaviour.
- Jul 13, 2026 Structural Hazards and the Cost of Duplicated Resources When two instructions in flight want the same hardware in the same cycle, and how port replication, banking, and arbitration each buy the conflict away at a different price.
- Jul 2, 2026 Immediate Encoding and How Arbitrary Constants Get Materialized Why an instruction can hold only a small constant, how sign extension and scaled fields are packed into the word, and the instruction sequences that build a full-width value.
- Jun 15, 2026 Virtualizing Accelerators Without Hardware Partitioning How software emulation, mediated passthrough, and API remoting differ, what each costs in exits, and why a device with a single register window resists sharing.
- Jun 12, 2026 Memory-Mapped Registers and the Ordering Rules Behind a Store How a device BAR becomes an address the core can load and store, why a posted write is not a completed write, and what a read-back actually guarantees.
- May 13, 2026 Misprediction Recovery: Checkpoints, Squash, and the Cost of Being Wrong How an out-of-order core unwinds speculative state when a branch resolves wrong, why checkpoints of the rename map beat walking a reorder buffer, and what limits recovery speed.
- May 13, 2026 Static Branch Prediction and the Branch Delay Slot How compilers and instruction sets answered the control hazard before dynamic predictors existed, and why delay slots were abandoned once pipelines got deeper.
- May 13, 2026 The Reorder Buffer and In-Order Retirement How entries move through the reorder buffer from allocation to commit, why retirement order is what makes speculative and out-of-order execution safe, and what limits the buffer size.
- May 5, 2026 Register File Ports and Operand Delivery Why each extra read port on a register file costs area, latency, and energy, how banking and replication spread the cost, and what late operand collection buys a wide-issue machine.
- May 4, 2026 Load-Store Ordering and Memory Disambiguation in a Speculative Machine Why loads may run ahead of stores, how the memory order buffer checks addresses it does not know yet, and what happens when a load guesses wrong.
- Apr 28, 2026 Store Buffers and the Total Store Order That Replaces Sequential Consistency How a per-core store buffer hides cache-miss latency, exactly which four orderings TSO keeps, and why load-load reordering is forbidden while load-store is not.
- Apr 25, 2026 Control Hazards: What a Branch Costs Before It Resolves The cycles a taken branch throws away in a five-stage pipeline, why the penalty equals the number of fetches in flight, and how prediction turns a fixed loss into a probabilistic one.
- Apr 17, 2026 Cache Coherence Is Per Location, Consistency Is Not Why a machine can agree perfectly on the order of writes to every individual address and still produce an execution with no single global ordering.
- Apr 1, 2026 Mask Registers, Tail Handling, and the Cost of the Last Iteration How per-lane execution masks replace the scalar remainder loop, what inactive lanes still consume, and why vector length control and tail policy decide whether the last iteration is cheap.
- Mar 19, 2026 Precise Exceptions from an Imprecise Machine Why an out-of-order core must present exceptions at exact instruction boundaries, the ordering rules for synchronous faults versus interrupts, and what the operating system can rely on.
- Mar 12, 2026 Scheduling and Preemption on Accelerator Queues Why a device queue is a scheduling entity, how hardware contexts make preemption possible, and what mid-kernel eviction costs when the device has no save state.
- Mar 4, 2026 The Power Wall: Why Frequency Scaling Stopped How dynamic power depends on voltage and frequency, why Dennard scaling ended when the supply voltage stopped falling, and what replaced clock rate as the source of throughput.
- Feb 28, 2026 Front-End Throughput and the Fetch Bandwidth Ceiling Why a wide out-of-order back end can still run narrow, how instruction cache line boundaries, prediction, and decode width bound the supply, and what designs do about it.
- Feb 25, 2026 Heterogeneous Cores and the Area-Performance Frontier Why a large core and a small core can be combined to beat either alone, how area efficiency curves determine the mix, and what thread migration costs.
- Feb 22, 2026 Two-Operand Encodings and the Destructive Write Problem Why the second source register disappears in a two-operand format, how destructive writes constrain register allocation, and what a three-operand format buys back.
- Feb 20, 2026 Geometric History Lengths in TAGE Predictors How TAGE uses several tables with exponentially different history lengths, tagged entries, and a usefulness counter to pick the longest matching prediction without collapsing into aliasing.
- Feb 9, 2026 Forwarding Paths and the Load-Use Stall That Survives Them How bypass multiplexers supply an ALU result to a consumer before write-back, why a load cannot be forwarded the same way, and how the one-cycle bubble is detected.
- Dec 29, 2025 Clock and Power Gating: Computing the Break-Even Point How gating removes switching power from idle units, what state retention and inrush current cost, and the idle duration at which each form of gating starts to pay.
- Dec 17, 2025 Device DMA and the IOMMU Boundary What a device must be given before it can write to host memory, how an IOMMU turns a device address into a machine address, and what that translation costs.
- Dec 16, 2025 Initiation Interval and the Recurrence That Caps Throughput Why a loop with a circular dependency cannot be pipelined faster than its critical cycle allows, and how resource limits and latency combine into a minimum initiation interval.
- Nov 24, 2025 Fixed-Width Instruction Encoding and Where the Fields Go How a 32-bit instruction divides into opcode, register and immediate fields, why the register fields keep the same bit offsets across formats, and what that costs in reachable constants.
- Oct 26, 2025 Fixed-Width SIMD Lanes Versus Scalable Vector Registers Why one design bakes the vector length into the instruction encoding and the other reports it at run time, and how each choice propagates into code generation, binary compatibility, and register pressure.
- Oct 26, 2025 Vector Chaining and What It Costs in the Register File How forwarding a vector result element by element to a dependent operation cuts latency from the sum of stage latencies to the last stage alone, and why chain slots rather than arithmetic units bind performance.
- Oct 24, 2025 Opcode Space Allocation and How Extensions Claim Encodings How an instruction set divides its opcode map among base operations, extensions and vendor additions, and what happens when the map runs out of room.
- Oct 17, 2025 Retiming and Balancing the Stages of a Datapath How logic is moved across pipeline registers to shorten the longest stage, which moves are legal, and why a balanced pipeline is a fixed-point problem rather than a partition.
- Sep 15, 2025 What a Fence Instruction Actually Does to the Pipeline The three mechanisms behind fence cost — buffer drain, request acknowledgement, and memory-operation serialisation — and why a fence is never a cache flush.
- Sep 3, 2025 Strided, Indexed, and Gather Memory Access Why contiguous vector loads map onto ordinary cache lines while strided and indexed accesses turn into many element transactions, and where the memory system stops being able to keep a vector unit fed.
- Aug 20, 2025 Loop Dependences and What Blocks Vectorisation Why a loop that looks parallel to a reader is often sequential to a compiler, which dependences forbid combining iterations, and how runtime checks and reductions recover part of what static analysis loses.
- Jun 15, 2025 Speculative Execution and the Architectural Side Effects of a Wrong Guess Squashing removes speculative state from the architecture but not from caches, predictors, and timing; how that residual state becomes an observable channel and what mitigation costs.
- Jun 9, 2025 Checkpointing and Recovery from Misprediction How a speculative machine restores an exact rename mapping after a wrong branch, why per-branch checkpoints beat a walk-back repair, and what recovery latency costs.
- Jun 1, 2025 Shared Virtual Addressing and Peer-to-Peer Transfers What changes when a device uses the process page table directly, why a PASID is needed, and what must happen before one device writes into another device's memory.
- May 30, 2025 Simultaneous Multithreading and the Slots It Fills How several threads share one out-of-order pipeline, which structures must be replicated to make that useful, and why adding a second thread buys less than doubling the issue width.
- May 17, 2025 Aliasing, Tournament Predictors, and Per-Branch Selection When two predictor tables disagree, a choice predictor decides which to believe; the mechanics of tagged entries, confidence counters, and the cost of mispredicting the chooser itself.
- May 4, 2025 Interrupt Moderation and Event Delivery at High Rates Why one interrupt per completed transfer collapses at high packet rates, how coalescing timers and counters bound the damage, and what a polled-mode driver gives up.
- Apr 30, 2025 Software Pipelining and Loop-Carried Dependences How modulo scheduling overlaps iterations of a loop, why the recurrence constraint sets a hard lower bound on cycles per iteration, and how unrolling and register pressure limit the schedule.
- Mar 27, 2025 Data Movement as the Real Bottleneck in Offload Design How to account for the bytes an offload costs, which boundary dominates at each scale, and why the offload with the best local speedup is often the wrong one.
- Feb 24, 2025 Decode Bandwidth and the Cost of Variable Instruction Length Why fixed-width instructions let a front end decode several per cycle, how variable-length encodings force serial scanning, and where the two approaches land on fetch and decode throughput.
- Dec 24, 2024 Issue Width and the Structural Ceiling on Instructions per Cycle How a superscalar core decides how many instructions to start per cycle, which pipeline stage usually sets the limit, and why a four-wide machine rarely retires four instructions per cycle.
- Nov 3, 2024 Value Prediction and the Limits of Speculating on Data What it would take to break true data dependencies, why value prediction attacks a different limit than branch prediction, and the correctness and cost barriers that keep it out of shipping cores.
- Oct 24, 2024 Systolic Arrays and Dataflow Scheduling How a grid of multiply-accumulate cells reuses operands by moving them between neighbours, why the schedule is the compiler's job, and where the approach stops paying.
- Sep 16, 2024 Descriptor Rings and the Producer-Consumer Contract How a ring buffer carries work from a driver to a device without locks, what the ownership bit buys, and why the wrap-around index is the hard part.
- Sep 12, 2024 Addressing Modes and How an Effective Address Is Computed How base, index, scale and displacement fields combine into an address, why some ISAs fold memory operands into arithmetic, and what each mode costs in the datapath.
- Jul 17, 2024 The Area Budget: Reticle Limits, Yield, and Cost per Die Why a die cannot grow past the lithography field, how defect density makes cost superlinear in area, and what a square millimetre of silicon actually buys.
- Jul 10, 2024 VLIW Bundles and the Compiler as Scheduler How very long instruction word machines move dependence checking and slot assignment into the compiler, what that buys in hardware, and why exposed pipeline latency and binary compatibility make the trade expensive.
- May 31, 2024 Condition Codes, Flag Registers and the Dependency They Create How comparison results become flags, why an implicit flag register serialises code, and how architectures that compare directly into registers avoid the hazard.
- Apr 29, 2024 Chiplets and the Cost of Leaving the Die What partitioning buys in yield and reticle headroom, and what the die-to-die interface costs in energy per bit, latency, and package complexity.
- Apr 16, 2024 Interlocks, Bubbles, and How a Stall Propagates Backwards How a pipeline detects a dependency in hardware, freezes the stages behind it, and injects a no-operation, including the reason a stall must be signalled backwards and not forwards.
- Mar 24, 2024 SIMD Encoding: Vector Register Fields, Predication and Length How vector instructions spend their encoding bits on register numbers, masks and element widths, and why vector length is sometimes in the instruction and sometimes in a control register.
- Jan 30, 2024 Delay Slots and the Burden They Move to the Compiler Why some architectures require the instruction after a branch to execute unconditionally, which instructions are legal in that slot, and what the scheduler must prove before filling it.
- Jan 22, 2024 Sequential Consistency and the Cost of One Global Memory Order What Lamport's definition of sequential consistency requires of a machine, which reorderings it forbids, and why every commercial processor relaxes it.
- Oct 18, 2023 Global History and the Gshare Index Hashing recent branch outcomes into the predictor index lets one branch learn from another; the mechanism, the XOR that spreads history across sets, and the interference it creates.
- Oct 7, 2023 ISA Families, Extension Levels and Binary Compatibility How architectures partition optional instructions into named levels, how a binary discovers what the current processor implements, and where forward compatibility quietly breaks.
- Oct 6, 2023 Register Renaming and the Elimination of False Dependencies Why architectural register names serialize otherwise independent code, how a rename table maps names to physical registers, and what the mapping costs in area and latency.
- Aug 28, 2023 Ordering Across the Device Boundary: DMA, MMIO, and Posted Writes Why a device can read stale data after a synchronising store, how posted writes hide completion, and which barriers cross the boundary in each direction.
- Aug 22, 2023 Deep Pipelines and Why More Stages Stop Paying The arithmetic of latch overhead, the growing penalty for branches and exceptions, and the point at which another stage costs more throughput than it returns.
- Jun 6, 2023 The Five-Stage Pipeline and the Throughput It Buys Why splitting a datapath into five stages raises instruction throughput without shortening any single instruction, and what latch overhead and stage imbalance take back.
- Apr 19, 2023 Precise Exceptions and Restarting a Pipeline Mid-Stream Why a pipeline must be able to name one instruction as the faulting one, and how the commit point, the in-flight register file, and the restart PC are made consistent.
- Mar 22, 2023 How a Branch Target Buffer Delivers the Target in the Fetch Cycle The BTB supplies a taken branch target before decode, which requires predicting the address as well as the direction and creates its own tagging, aliasing, and coherence problems.
- Feb 8, 2023 Specialisation as an Energy Strategy Why a fixed-function unit beats a general-purpose core on energy per operation, how Amdahl and utilisation bound the payoff, and what the built-in generality of a core is worth.
- Dec 13, 2022 Sizing the Window: Why More Entries Stop Paying The diminishing returns of a larger instruction window, the queueing model that explains them, and the second-order effects that make big windows expensive.
- Nov 11, 2022 The Cost of Generality: Why Fixed-Function Logic Wins What a programmable core spends on instruction issue and operand fetch, how Amdahl bounds the payoff of offloading work, and where a fixed-function unit actually beats a CPU.
- Jul 14, 2022 Two-Bit Saturating Counters and the Bimodal Predictor Why a two-bit hysteresis counter beats a single bit for branch prediction, how the index is computed, and where the table fails: aliasing, short loops, and correlated branches.
- Jun 3, 2022 Why an In-Order Pipeline Stalls and What an Instruction Window Buys How dependencies, latency, and a fixed instruction supply bound an in-order pipeline, and why a sliding window of decoded instructions is the cheapest way out.
- May 12, 2022 The Control Hazard and Why Fetch Must Guess the Next Instruction How a pipelined front end turns every branch into a bet, what a wrong bet costs in cycles, and why stalling instead of guessing is worse than it looks.
- Feb 11, 2022 Return Address Stacks and the Prediction of Indirect Branches Why returns and indirect jumps cannot be predicted from address history alone, how a call stack mirror in the fetch unit handles returns, and what indirect predictors store instead.