Computer Architecture · Cluster
Superscalar and Vector
Wide issue and data-parallel execution.
- 01 Issue Width and the Structural Ceiling on Instructions per Cycle How a superscalar core decides how many instructions to start per cycle, which pipeline stage usually sets the limit, and why a four-wide machine rarely retires four instructions per cycle.
- 02 VLIW Bundles and the Compiler as Scheduler How very long instruction word machines move dependence checking and slot assignment into the compiler, what that buys in hardware, and why exposed pipeline latency and binary compatibility make the trade expensive.
- 03 Fixed-Width SIMD Lanes Versus Scalable Vector Registers Why one design bakes the vector length into the instruction encoding and the other reports it at run time, and how each choice propagates into code generation, binary compatibility, and register pressure.
- 04 Register File Ports and Operand Delivery Why each extra read port on a register file costs area, latency, and energy, how banking and replication spread the cost, and what late operand collection buys a wide-issue machine.
- 05 Software Pipelining and Loop-Carried Dependences How modulo scheduling overlaps iterations of a loop, why the recurrence constraint sets a hard lower bound on cycles per iteration, and how unrolling and register pressure limit the schedule.
- 06 Vector Chaining and What It Costs in the Register File How forwarding a vector result element by element to a dependent operation cuts latency from the sum of stage latencies to the last stage alone, and why chain slots rather than arithmetic units bind performance.
- 07 Mask Registers, Tail Handling, and the Cost of the Last Iteration How per-lane execution masks replace the scalar remainder loop, what inactive lanes still consume, and why vector length control and tail policy decide whether the last iteration is cheap.
- 08 Simultaneous Multithreading and the Slots It Fills How several threads share one out-of-order pipeline, which structures must be replicated to make that useful, and why adding a second thread buys less than doubling the issue width.
- 09 Strided, Indexed, and Gather Memory Access Why contiguous vector loads map onto ordinary cache lines while strided and indexed accesses turn into many element transactions, and where the memory system stops being able to keep a vector unit fed.
- 10 Loop Dependences and What Blocks Vectorisation Why a loop that looks parallel to a reader is often sequential to a compiler, which dependences forbid combining iterations, and how runtime checks and reductions recover part of what static analysis loses.