Computer Architecture · Cluster
Memory Consistency
Ordering rules and fence semantics.
- 01 Sequential Consistency and the Cost of One Global Memory Order What Lamport's definition of sequential consistency requires of a machine, which reorderings it forbids, and why every commercial processor relaxes it.
- 02 Cache Coherence Is Per Location, Consistency Is Not Why a machine can agree perfectly on the order of writes to every individual address and still produce an execution with no single global ordering.
- 03 Store Buffers and the Total Store Order That Replaces Sequential Consistency How a per-core store buffer hides cache-miss latency, exactly which four orderings TSO keeps, and why load-load reordering is forbidden while load-store is not.
- 04 Acquire and Release as One-Way Ordering Constraints How a release store and an acquire load each constrain ordering in only one direction, and why the pair is enough to publish data without a full fence.
- 05 What a Fence Instruction Actually Does to the Pipeline The three mechanisms behind fence cost — buffer drain, request acknowledgement, and memory-operation serialisation — and why a fence is never a cache flush.
- 06 Litmus Tests and How Allowed Outcomes Are Decided How a few lines of concurrent code pin down a memory model, how tools enumerate the executions, and why "never observed" is weaker than "forbidden".
- 07 Read-Modify-Write Atomicity and the Ordering It Carries Why an atomic increment cannot be built from a load and a store, what compare-and-swap costs in coherence traffic, and how an atomic operation acts as a fence.
- 08 Propagation, Cumulativity, and Why Weak Models Need Transitive Visibility Messages that preserve ordering are not enough: a store already observed by one thread must be observed by every thread it reaches, and multi-copy atomicity is the property that says so.
- 09 Compiler Reordering and the Contract It Must Not Break Why an optimiser may sink an atomic load past a store only in certain cases, where the as-if rule stops, and how data races turn a performance model into undefined behaviour.
- 10 Ordering Across the Device Boundary: DMA, MMIO, and Posted Writes Why a device can read stale data after a synchronising store, how posted writes hide completion, and which barriers cross the boundary in each direction.