The Area Budget: Reticle Limits, Yield, and Cost per Die

Every architecture proposal eventually meets a number in square millimetres. Adding a fourth floating-point pipeline, doubling the last-level cache, or widening the issue window all consume the same resource, and that resource is bounded from three independent directions: the lithography tool cannot expose an arbitrarily large field, the probability that a die contains no defect falls exponentially with area, and the package has to deliver power and remove heat from whatever area exists. The first two set what is manufacturable and affordable; the third sets what is usable.

Because the three limits bind at different points, the area budget is not one number but a curve, and the shape of that curve is why chip design since the mid-2010s has been a story about partitioning.

The reticle field is a hard geometric ceiling

A photolithographic exposure projects a mask through a stepper’s reduction lens. The illuminated field of a modern 193 nm scanner is roughly 26 mm by 33 mm, and one exposure covers that rectangle. A die larger than the field cannot be printed in a single pass; it must be stitched from two or more exposures, with the pattern aligned across the boundary to a small fraction of the smallest feature. Stitching works, and it has been used for large dies, but it costs yield and throughput and constrains where wires may cross the seam.

For most designs the field is not a limit that gets approached, it is a limit that gets avoided, and the practical ceiling on a monolithic die is somewhat below it because the scribe lanes and edge structures consume part of the field. The consequence is a hard wall: once a design reaches the field size, the only way to add function is to add a second die. That wall is what made multi-die packaging a mainstream option rather than an exotic one, as discussed in Chiplets and the Cost of Leaving the Die.

Cost per die grows faster than area

A wafer is priced per wafer, not per good die, so the cost of a working part is the wafer cost divided by the number of usable dies it yields. Two effects make that division unfavourable as area grows.

The first is geometric and mild. The number of full dies that fit on a circular wafer of diameter $d$ is approximately

$$N \approx \frac{\pi (d/2)^2}{A} - \frac{\pi d}{\sqrt{2A}}$$

where $A$ is the die area. The first term is the area ratio; the second subtracts the partial dies along the circumference. Doubling $A$ roughly halves $N$, minus a little more for the edge loss, so cost per die roughly doubles.

The second effect is not mild. A wafer has some density of point defects per unit area, call it $D_0$, arising from particles, mask errors, and process excursions. If defects were distributed randomly and independently, the probability that a die of area $A$ contains none of them would be $e^{-A D_0}$. The exponential is the problem: at a defect density where a 50 mm² die yields 90 percent, a 200 mm² die of the same process yields about 66 percent, and a 400 mm² die about 43 percent. Real yield models are kinder than pure Poisson because defects cluster, and the Murphy model and the negative binomial model both flatten the curve, but the direction holds: doubling area more than doubles cost per good part.

import math

def dies_per_wafer(diameter_mm, area_mm2):
    r = diameter_mm / 2
    return math.pi * r * r / area_mm2 - math.pi * diameter_mm / math.sqrt(2 * area_mm2)

def poisson_yield(area_mm2, defects_per_mm2):
    return math.exp(-area_mm2 * defects_per_mm2)

for area in (50, 100, 200, 400):
    n = dies_per_wafer(300, area)
    y = poisson_yield(area, 0.0021)
    print(area, round(n), round(y, 3), round(n * y))

The last column is good dies per 300 mm wafer. It rises with area far more slowly than the area itself, which is the whole economic argument: at a fixed defect density, a die of twice the area is more than twice as expensive per working part, because the yield it loses is a second factor on top of the area it doubles. The size of that penalty depends on $D_0$: at the density used here, a 400 mm² die costs about 19 times what a 50 mm² die costs per good part against an 8× area ratio, and the factor falls toward 8 as the process matures and $D_0$ approaches zero.

This is why the same process node ships both small mobile parts and large server parts, and why the server part costs several times what its area ratio would suggest. It is also why defect tolerance techniques matter: a last-level cache with spare ways that can be fused off after test converts some fraction of defective dies into sellable ones, which changes the yield curve rather than the area budget.

What a square millimetre buys

The area cost of a feature is what determines whether it is worth having, and the units differ wildly between structures.

SRAM is the densest thing on a logic die. A six-transistor bit cell occupies on the order of one hundred square feature units, so a 64 KiB array at a modern node is a small fraction of a square millimetre, while a 32 MiB last-level cache is a substantial one. Because cache area scales linearly with capacity while its benefit scales with the miss rate it removes, the marginal value of cache falls steeply: doubling from 1 MiB to 2 MiB removes many more misses than doubling from 32 MiB to 64 MiB, and costs the same area both times.

A functional unit is a much larger commitment. An integer ALU with its bypass network is small; a floating-point fused multiply-add pipeline with a full IEEE 754 rounding path is an order of magnitude larger; a vector unit wider than the register file can feed is larger still, because the register file, the bypass multiplexers, and the load-store path all scale with width. Widening an issue width from four to six instructions per cycle does not cost 50 percent more area in the scheduler alone; the wakeup and select logic grows faster than linearly with the number of entries, and the bypass network grows with the square of the number of producers, which is the constraint Issue Width and Its Diminishing Returns quantifies.

A third category is nearly free in area but expensive in verification and in schedule: control logic, decoders, and anything with an irregular structure. Their transistor count is small and their design cost is not.

Area is a power decision wearing a different hat

Leakage current flows per transistor, so a larger die leaks more, and the relationship is roughly linear in area at a fixed supply and temperature. A design that spends its area on cache gets a structure that is dense but leaky per bit; a design that spends it on wide execution gets a structure that is both leaky and switching. Either way the area budget and the power budget are the same budget seen from two sides, which is why Power Density and the Dark Silicon Constraint frames the problem as one of utilising area rather than acquiring it.

The thermal path adds a third constraint that is not proportional to area at all. Heat spreads laterally through the silicon and the package, so a small hot spot is worse than the same power spread over a large area. Placing a wide vector unit next to a memory controller, both of which switch hard, creates a local power density that the package cannot relieve, and the fix is physical separation that costs wiring delay. Floorplanning is therefore part of the architecture, not an implementation detail, and the placement decision shows up as a frequency limit rather than as an area number.

Why partitioning changes the arithmetic

Splitting a design into several smaller dies attacks the yield term directly. Four 100 mm² dies each yield better than one 400 mm² die, and the reticle field no longer binds. The costs are real: die-to-die interfaces consume area and power on both sides, the package becomes more expensive, and a die that fails test takes its neighbours’ yield with it only if the assembly is done before test, which is why known-good-die testing exists.

The economics therefore depend on defect density, package cost, and how much of the design can be cleanly divided. A design that is naturally partitioned, such as repeated compute tiles with a shared memory system, splits well. A design whose critical path crosses the whole chip, such as a monolithic out-of-order core, does not, because the split adds latency exactly where latency is already the binding constraint.

The general rule is that partitioning pays when the area saved by better yield exceeds the area and power spent on the interfaces, and that calculation has shifted toward partitioning as defect densities at advanced nodes have become harder to drive down. It is the same trade, at a different scale, as the one between a large cache and a small cache plus a memory-side structure: the resource being budgeted is not silicon but the product of silicon, yield, and the latency the partitioning introduces.