Power Density and the Dark Silicon Constraint

Under Dennard scaling a chip’s power density stayed constant as transistors shrank, so each generation could double the transistor count at the same clock and the same power. Once the supply voltage stopped falling, that relationship inverted. Transistor density continued to double per node while the energy per switching event fell only modestly, so a chip built at the new node could hold twice as many transistors but could only afford to switch a fraction of them.

That fraction is the constraint usually called dark silicon. The name suggests unused area, and the useful way to read it is not as area that must stay idle but as area that must stay idle at full clock at the nominal voltage. The constraint is about simultaneous activity, and it admits a large family of responses, most of which are now standard practice.

The arithmetic of the gap

Take a fixed die area and a fixed power budget. Suppose a design at one node uses $A$ mm² and dissipates $P$ watts at the maximum operating point. At the next node, transistor density roughly doubles, so the same function fits in $A/2$ mm², or the same $A$ holds twice the function. The power per unit of switched capacitance improves only modestly, because the capacitance per transistor falls with the feature size but the voltage no longer falls with it. So a design that fills the new die with twice the switching activity wants roughly twice the power, and the budget does not allow it.

The usable fraction is therefore approximately

$$f_{\text{active}} \approx \frac{P_{\text{budget}} / A}{P_{\text{density,new node}}}$$

If the new node’s full-activity power density is twice the budget, half the area can be active at once. If it is three times, a third. The estimates in the 2011 literature put the fraction in the range where a large share of a future die could not be used at full clock, and the fraction worsens with each node unless the operating point or the activity changes.

Two caveats matter for reading those estimates. The power density figure depends on what the transistors are doing: an SRAM array is far denser and far less power hungry per bit than an execution pipeline, so a chip that spends its area on cache is much less constrained than one that spends it on arithmetic. And the budget is not fixed, because DVFS lowers both power and performance together, so “cannot be active” is shorthand for “cannot be active at the highest operating point”.

Idle is not the only response

The naive reading of dark silicon is that a fixed fraction of the chip must be switched off. Four responses are used in practice, and they compose.

Specialisation. Instead of filling the die with identical general-purpose cores, fill it with heterogeneous units, each of which is far more efficient at its task than a general core would be. A video decoder built as fixed-function logic uses a small fraction of the energy per frame that the same work costs on a wide out-of-order core, because it does not fetch, decode, rename, and schedule instructions for every pixel. The die is fully populated, but at any moment only the units relevant to the current workload are active, so the active fraction stays inside the power budget while the area is doing useful work. This is the argument that made accelerators mainstream and is developed in Specialisation as an Energy Strategy.

Time multiplexing. Run the general-purpose cores below their maximum operating point most of the time and boost a subset when the workload allows. The area is fully used, but not all at full speed at once. This is the same token-bucket mechanism described in Thermal Design Power, applied per core rather than per package.

Near-threshold operation. Lower the supply toward the threshold voltage, which cuts switching energy quadratically but slows the circuit. Many slow cores at low voltage can outperform a few fast ones at the same power, provided the workload is parallel. This is the extreme end of the frequency-versus- parallelism trade in The Power Wall, and it is the operating regime that heterogeneous designs exploit for background work.

Memory-side spending. Move work to structures that are cheap in energy per bit, such as caches and specialised memory-side compute. A last-level cache consumes a small fraction of the power per millimetre that a logic pipeline does, so a die weighted toward memory is less constrained and, for memory-bound workloads, faster as well.

Why specialisation beats width

The reason a specialised unit wins is not that its logic is smaller. It is that the general-purpose core’s energy is dominated by overhead that the specialised unit does not pay.

Every instruction a general core executes costs instruction fetch, decode, register renaming, issue, bypass network activity, and retirement, regardless of how much arithmetic the instruction performs. Those structures switch on every cycle and they are a large share of the core’s power. A wide out-of-order core spends a substantial part of its energy budget on moving instructions around rather than on computing, and widening it further increases the movement cost faster than the compute cost.

A specialised unit removes the movement. A fixed-function block that processes a block of pixels has no instruction stream to fetch, no rename map to update, and no reorder buffer to drain. The control logic is small and mostly idle, so the switching energy goes to the arithmetic that the workload actually needs.

The trade is that the specialised unit does nothing for other workloads. Its area is spent, and its power is only justified when the workload uses it. If the workload mix shifts, the area is wasted in a way that a general core’s area is not. That is the bet: a chip with many specialised units performs extremely well on the mixes it was designed for and poorly on the ones it was not, and the design process is a forecast of the mix.

# Illustrative energy comparison, not a measurement. Per unit of work,
# a general core pays instruction-supply overhead the fixed unit does not.
def general_core_energy(ops, p_fetch, p_decode, p_execute, cycles_per_op=4):
    return ops * cycles_per_op * (p_fetch + p_decode + p_execute)

def fixed_function_energy(ops, p_datapath, cycles_per_op=1):
    return ops * cycles_per_op * p_datapath

# The ratio is dominated by how much of the general core is overhead,
# which is why the specialised block wins by several times rather than
# by a few percent.
print(general_core_energy(1e6, 0.4, 0.3, 1.0) / fixed_function_energy(1e6, 1.2))

What the constraint does to scheduling

If only a fraction of the die can be active at the highest operating point, the operating system’s scheduler becomes part of the power architecture. Placing work on the units that are most efficient for it, and keeping the rest gated, is worth more than any microarchitectural tweak. The mechanisms are described in Heterogeneous Cores: the scheduler needs to know each unit’s efficiency curve, and the hardware needs to expose it.

The failure mode is a workload that does not match the forecast. A chip with a large accelerator and a small general core performs badly on code that the accelerator cannot take, because the general core is sized for the common case rather than the peak. If the accelerator’s share of the mix falls, the die is carrying area that cannot help. Architectures respond by making the accelerator programmable and by keeping the general core capable enough to run the fallback path, which is a hedge against the forecast being wrong and costs area that could have gone to the accelerator.

A second failure mode is thermal, not average-power. Dark silicon reasoning uses an average power density, but heat is generated locally. A small accelerator running flat out creates a hot spot that the package cannot spread, so its sustained operating point is lower than its average-power analysis suggests. That is why floorplanning places high-power units apart and why The Area Budget treats placement as an architectural decision.

The constraint is not a law

Dark silicon is an argument about a specific regime: fixed supply voltage, fixed die area, fixed cooling. Change any of those and the fraction changes.

Advanced packaging changes the area term, because a design can spread over several dies and the power per die falls even though the total transistor count rises. That is one of the reasons chiplets became attractive, as described in Chiplets and the Cost of Leaving the Die.

Better cooling changes the budget, but only within the limits of the package and the facility. Liquid cooling raises the power a given area can dissipate, and it does so at a cost that is paid in infrastructure rather than in silicon.

Workload changes dominate both. A chip that is idle most of the time is not dark; it is gated, and its average power is far below its peak. The constraint bites for workloads that want everything at once, and those are exactly the workloads for which the architecture is designed. The honest statement is that the peak operating point of a large die is set by power, that sustained throughput is set by the mix of active units, and that the design problem is choosing which units to build so that the mix lands inside the budget.