Clock and Power Gating: Computing the Break-Even Point

A processor that is waiting on a cache miss still burns power. The pipeline registers keep toggling against the stalled instruction, the clock tree distributes a square wave to every flip-flop in the block, and every transistor on the supply leaks whether or not it is doing anything. Since the arithmetic in The Power Wall makes the switching term quadratic in voltage, the cheapest way to reduce it is to stop switching altogether, and the two mechanisms for doing so differ in what they can turn off and what they must pay to turn back on.

The interesting part is not that gating saves energy. It is that gating has a fixed cost, and below a certain idle duration the cost exceeds the saving.

Clock gating removes the switching term without losing state

The clock is the single largest net on a synchronous chip. It reaches essentially every sequential element, it switches on every cycle by construction, and its wires are long, so its capacitance is large. Distribution networks for the clock commonly account for a substantial share of total dynamic power on a high-performance core, with published estimates in the range of a quarter to a third of the chip’s switching power.

Clock gating stops the toggling at the root of a subtree. The straightforward implementation is an AND gate in the clock path with an enable signal, but a bare AND gate produces glitches: if the enable changes while the clock is high, the gate output can produce a runt pulse that latches a flip-flop into an unintended state. The standard structure therefore places a level-sensitive latch on the enable, transparent while the clock is low, so the enable can only change during the low phase and the gated clock is either a clean copy of the input or a constant zero.

// Integrated clock gate: enable sampled while clk is low, so the
// gated output can never produce a runt pulse.
module icg (input clk, input enable, output gclk);
  reg en_latched;
  always @(*) begin
    if (!clk) en_latched = enable;   // latch, transparent when clk is low
  end
  assign gclk = clk & en_latched;
endmodule

The saving is exact: a gated subtree dissipates no clock power at all, and its flip-flops hold their values, so nothing has to be saved or restored. The cost is the gate itself, the latch, and the enable logic, which is a few tens of transistors per gated subtree, and the design effort of deciding when to gate.

Granularity is the trade. A single coarse gate on the whole core is trivial to build and useless when the core is doing partial work. Fine-grained gating at the level of a functional unit or a register bank saves more but requires per-unit idle detection, and the detection logic itself switches. In practice gating is hierarchical: the unit’s clock is gated when the unit has no instruction in flight, and the sub-block’s clock is gated when its local pipeline is empty, with the enable signals derived from existing valid bits rather than from new comparators.

Automatic gating insertion by synthesis tools handles most of this, because the condition “this register’s next value equals its current value” is exactly the condition under which it need not be clocked. That is why gating scales with design size without a matching growth in hand-written control.

Power gating removes leakage and must reconstruct state

Clock gating leaves the block on the supply, so it removes dynamic power and nothing else. Leakage remains, and at advanced nodes leakage is a large enough share of the budget that an idle block is still expensive. Power gating attacks that term by inserting a switch between the block and one of the supply rails, typically a header transistor to the high rail or a footer to the low rail, and turning the switch off so the block floats.

Three problems follow immediately, and each has a standard solution with a standard cost.

The first is state. A gated block loses every value in its flip-flops, so either the block’s state is saved to an always-on memory before shutdown and restored after, or the flip-flops are replaced with retention cells that hold their value from a separate always-on supply. Retention cells cost area in every bit they are used for and still leak, just less; saving to memory costs energy proportional to the state size and takes time proportional to the transfer. A block with a large architectural state, such as a vector register file, is expensive to power gate for this reason, and a block with a small state, such as an arithmetic pipeline whose contents are discarded on flush, is cheap.

The second is isolation. While the block floats, its outputs are indeterminate, and a downstream block that is still powered will see them as valid signals and can latch garbage or, worse, draw crowbar current through a complementary input stage held at an intermediate voltage. Isolation cells clamp the block’s outputs to a defined level while it is off. They are small but they sit on every signal that crosses the boundary, and their count grows with the interface width rather than with the block’s size.

The third is inrush. Turning on a header switch connects a discharged block’s decoupling capacitance to the supply through a transistor with finite resistance, so the current spike is large. Inrush current causes resistive drop on the shared supply, which can disturb neighbouring blocks, and it causes electromigration stress on the switch itself. The fix is a daisy chain of switches turned on in sequence, which lengthens the wake-up time.

The break-even calculation

Let $P_{\text{saved}}$ be the power the block consumes while active and $P_{\text{leak}}$ be what it consumes while gated, which for clock gating is the leakage and for power gating is the retention cell leakage. Let $E_{\text{over}}$ be the one-time energy of the transition, including the save and restore transfer, the isolation and clamp activity, and the inrush charge. Gating for a duration $t$ pays when

$$(P_{\text{saved}} - P_{\text{gated}}) , t > E_{\text{over}}$$

so the break-even time is $E_{\text{over}} / (P_{\text{saved}} - P_{\text{gated}})$.

Clock gating has a break-even near zero, because $E_{\text{over}}$ is a handful of gate transitions and there is nothing to restore. A single idle cycle is enough. That is why clock gating is unconditional and pervasive.

Power gating has a break-even measured in hundreds of cycles to tens of microseconds, depending on the state size and the switch sequencing. A block that will be idle for a few hundred cycles should be clock gated and left powered; a block that will be idle for a millisecond should be power gated. Between those, the answer depends on how much state has to be moved and whether retention cells make the transfer unnecessary.

/* Choose a gating mode from a predicted idle duration. Thresholds are
 * policy parameters, calibrated per block against the break-even above. */
enum gate_mode { GATE_NONE, GATE_CLOCK, GATE_POWER };

enum gate_mode select_gate(unsigned idle_cycles, unsigned clock_be,
                           unsigned power_be) {
    if (idle_cycles < clock_be)  return GATE_NONE;   /* never worth it */
    if (idle_cycles < power_be)  return GATE_CLOCK;  /* saves switching only */
    return GATE_POWER;                               /* saves leakage too */
}

The prediction is the hard part. Idle duration is known only after it ends, so the controller must guess from history: a queue that has been empty for $n$ cycles is likely to stay empty, a unit that just finished a long burst is likely to be idle, and a unit waiting on a memory response is idle for a duration roughly equal to the miss latency, which is known. Predicting too eagerly wastes wake-up energy on intervals that turn out short; predicting too conservatively leaves leakage on the table. The cost of a wrong guess is asymmetric, which is why policies tend to be biased toward the cheap mistake.

Why the two mechanisms are layered, not alternatives

A real power-management stack uses both, in order of increasing latency and increasing saving. Clock gating is always on. Power gating is applied to blocks with long, predictable idle periods. Voltage and frequency scaling sits above both and is discussed in Voltage and Frequency Domains; the three form a hierarchy where each level costs more to enter and saves more once entered.

The hierarchy has a failure mode worth naming. A block that is power gated cannot respond to a request until its supply has settled and its state has been restored, so requests arriving during that window either stall or are routed elsewhere. If the wake-up latency exceeds the tolerance of the requesting unit, the block must be kept powered, which is why caches with retention and always-on queue structures exist at the boundary of power-gated regions. The architecture has to know which blocks can tolerate a wake-up and which cannot, and that decision propagates into the interface protocols rather than staying inside the power controller.

At the far end of the same trade, the number of blocks that may be powered at once is limited by the thermal and current budget, not by the gating logic. That constraint is what Power Density and the Dark Silicon Constraint formalises: gating is the mechanism that keeps an over-provisioned chip inside its power envelope, and the envelope itself comes from the package.