Computer Architecture · Cluster
Pipelining
Hazards, forwarding, and deep pipelines.
- 01 The Five-Stage Pipeline and the Throughput It Buys Why splitting a datapath into five stages raises instruction throughput without shortening any single instruction, and what latch overhead and stage imbalance take back.
- 02 Forwarding Paths and the Load-Use Stall That Survives Them How bypass multiplexers supply an ALU result to a consumer before write-back, why a load cannot be forwarded the same way, and how the one-cycle bubble is detected.
- 03 Structural Hazards and the Cost of Duplicated Resources When two instructions in flight want the same hardware in the same cycle, and how port replication, banking, and arbitration each buy the conflict away at a different price.
- 04 Control Hazards: What a Branch Costs Before It Resolves The cycles a taken branch throws away in a five-stage pipeline, why the penalty equals the number of fetches in flight, and how prediction turns a fixed loss into a probabilistic one.
- 05 Interlocks, Bubbles, and How a Stall Propagates Backwards How a pipeline detects a dependency in hardware, freezes the stages behind it, and injects a no-operation, including the reason a stall must be signalled backwards and not forwards.
- 06 Delay Slots and the Burden They Move to the Compiler Why some architectures require the instruction after a branch to execute unconditionally, which instructions are legal in that slot, and what the scheduler must prove before filling it.
- 07 Deep Pipelines and Why More Stages Stop Paying The arithmetic of latch overhead, the growing penalty for branches and exceptions, and the point at which another stage costs more throughput than it returns.
- 08 Precise Exceptions and Restarting a Pipeline Mid-Stream Why a pipeline must be able to name one instruction as the faulting one, and how the commit point, the in-flight register file, and the restart PC are made consistent.
- 09 Initiation Interval and the Recurrence That Caps Throughput Why a loop with a circular dependency cannot be pipelined faster than its critical cycle allows, and how resource limits and latency combine into a minimum initiation interval.
- 10 Retiming and Balancing the Stages of a Datapath How logic is moved across pipeline registers to shorten the longest stage, which moves are legal, and why a balanced pipeline is a fixed-point problem rather than a partition.